* Prevent request submission to the hardware until we have
         * completed the reset in i915_gem_reset_finish(). If a request
         * is completed by one engine, it may then queue a request
-        * to a second via its engine->irq_tasklet *just* as we are
+        * to a second via its execlists->tasklet *just* as we are
         * calling engine->init_hw() and also writing the ELSP.
-        * Turning off the engine->irq_tasklet until the reset is over
+        * Turning off the execlists->tasklet until the reset is over
         * prevents the race.
         */
-       tasklet_kill(&engine->execlists.irq_tasklet);
-       tasklet_disable(&engine->execlists.irq_tasklet);
+       tasklet_kill(&engine->execlists.tasklet);
+       tasklet_disable(&engine->execlists.tasklet);
 
        /*
         * We're using worker to queue preemption requests from the tasklet in
 
 void i915_gem_reset_finish_engine(struct intel_engine_cs *engine)
 {
-       tasklet_enable(&engine->execlists.irq_tasklet);
+       tasklet_enable(&engine->execlists.tasklet);
        kthread_unpark(engine->breadcrumbs.signaler);
 
        intel_uncore_forcewake_put(engine->i915, FORCEWAKE_ALL);
 
        if (WARN_ON(intel_guc_send(guc, data, ARRAY_SIZE(data)))) {
                execlists_clear_active(&engine->execlists,
                                       EXECLISTS_ACTIVE_PREEMPT);
-               tasklet_schedule(&engine->execlists.irq_tasklet);
+               tasklet_schedule(&engine->execlists.tasklet);
        }
 }
 
        spin_unlock_irq(&engine->timeline->lock);
 }
 
-static void i915_guc_irq_handler(unsigned long data)
+static void guc_submission_tasklet(unsigned long data)
 {
        struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
        struct intel_engine_execlists * const execlists = &engine->execlists;
 
        for_each_engine(engine, dev_priv, id) {
                struct intel_engine_execlists * const execlists = &engine->execlists;
-               execlists->irq_tasklet.func = i915_guc_irq_handler;
+               execlists->tasklet.func = guc_submission_tasklet;
                engine->park = i915_guc_submission_park;
                engine->unpark = i915_guc_submission_unpark;
        }
 
        }
 
        if (tasklet)
-               tasklet_hi_schedule(&execlists->irq_tasklet);
+               tasklet_hi_schedule(&execlists->tasklet);
 }
 
 static irqreturn_t gen8_gt_irq_ack(struct drm_i915_private *dev_priv,
 
        for_each_engine(engine, i915, id) {
                /* Flush the residual irq tasklets first. */
                intel_engine_disarm_breadcrumbs(engine);
-               tasklet_kill(&engine->execlists.irq_tasklet);
+               tasklet_kill(&engine->execlists.tasklet);
 
                /*
                 * We are committed now to parking the engines, make sure there
 
  * Check the unread Context Status Buffers and manage the submission of new
  * contexts to the ELSP accordingly.
  */
-static void intel_lrc_irq_handler(unsigned long data)
+static void execlists_submission_tasklet(unsigned long data)
 {
        struct intel_engine_cs * const engine = (struct intel_engine_cs *)data;
        struct intel_engine_execlists * const execlists = &engine->execlists;
 
        list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests);
        if (ptr_unmask_bits(p, 1))
-               tasklet_hi_schedule(&engine->execlists.irq_tasklet);
+               tasklet_hi_schedule(&engine->execlists.tasklet);
 }
 
 static void execlists_submit_request(struct drm_i915_gem_request *request)
 
        /* After a GPU reset, we may have requests to replay */
        if (execlists->first)
-               tasklet_schedule(&execlists->irq_tasklet);
+               tasklet_schedule(&execlists->tasklet);
 
        return 0;
 }
         * Tasklet cannot be active at this point due intel_mark_active/idle
         * so this is just for documentation.
         */
-       if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->execlists.irq_tasklet.state)))
-               tasklet_kill(&engine->execlists.irq_tasklet);
+       if (WARN_ON(test_bit(TASKLET_STATE_SCHED,
+                            &engine->execlists.tasklet.state)))
+               tasklet_kill(&engine->execlists.tasklet);
 
        dev_priv = engine->i915;
 
        engine->submit_request = execlists_submit_request;
        engine->cancel_requests = execlists_cancel_requests;
        engine->schedule = execlists_schedule;
-       engine->execlists.irq_tasklet.func = intel_lrc_irq_handler;
+       engine->execlists.tasklet.func = execlists_submission_tasklet;
 
        engine->park = NULL;
        engine->unpark = NULL;
 
        engine->execlists.fw_domains = fw_domains;
 
-       tasklet_init(&engine->execlists.irq_tasklet,
-                    intel_lrc_irq_handler, (unsigned long)engine);
+       tasklet_init(&engine->execlists.tasklet,
+                    execlists_submission_tasklet, (unsigned long)engine);
 
        logical_ring_default_vfuncs(engine);
        logical_ring_default_irqs(engine);
 
  */
 struct intel_engine_execlists {
        /**
-        * @irq_tasklet: softirq tasklet for bottom handler
+        * @tasklet: softirq tasklet for bottom handler
         */
-       struct tasklet_struct irq_tasklet;
+       struct tasklet_struct tasklet;
 
        /**
         * @default_priolist: priority list for I915_PRIORITY_NORMAL