extern int evergreen_rlc_resume(struct radeon_device *rdev);
 extern void rv770_set_clk_bypass_mode(struct radeon_device *rdev);
 
+/**
+ * r600_get_allowed_info_register - fetch the register for the info ioctl
+ *
+ * @rdev: radeon_device pointer
+ * @reg: register offset in bytes
+ * @val: register value
+ *
+ * Returns 0 for success or -EINVAL for an invalid register
+ *
+ */
+int r600_get_allowed_info_register(struct radeon_device *rdev,
+                                  u32 reg, u32 *val)
+{
+       switch (reg) {
+       case GRBM_STATUS:
+       case GRBM_STATUS2:
+       case R_000E50_SRBM_STATUS:
+       case DMA_STATUS_REG:
+       case UVD_STATUS:
+               *val = RREG32(reg);
+               return 0;
+       default:
+               return -EINVAL;
+       }
+}
+
 /**
  * r600_get_xclk - get the xclk
  *
 
        .mc_wait_for_idle = &r600_mc_wait_for_idle,
        .get_xclk = &r600_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = r600_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r600_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
        .mc_wait_for_idle = &r600_mc_wait_for_idle,
        .get_xclk = &r600_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = r600_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r600_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
        .mc_wait_for_idle = &r600_mc_wait_for_idle,
        .get_xclk = &r600_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = r600_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r600_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
        .mc_wait_for_idle = &r600_mc_wait_for_idle,
        .get_xclk = &rv770_get_xclk,
        .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
+       .get_allowed_info_register = r600_get_allowed_info_register,
        .gart = {
                .tlb_flush = &r600_pcie_gart_tlb_flush,
                .get_page_entry = &rs600_gart_get_page_entry,
 
                      struct radeon_ring *ring);
 void r600_gfx_set_wptr(struct radeon_device *rdev,
                       struct radeon_ring *ring);
+int r600_get_allowed_info_register(struct radeon_device *rdev,
+                                  u32 reg, u32 *val);
 /* r600 irq */
 int r600_irq_process(struct radeon_device *rdev);
 int r600_irq_init(struct radeon_device *rdev);