CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_FIFO_CLR);
 }
 
-static void vc4_crtc_config_pv(struct drm_crtc *crtc)
+static void vc4_crtc_config_pv(struct drm_crtc *crtc, struct drm_atomic_state *state)
 {
        struct drm_device *dev = crtc->dev;
        struct vc4_dev *vc4 = to_vc4_dev(dev);
        struct vc4_encoder *vc4_encoder = to_vc4_encoder(encoder);
        struct vc4_crtc *vc4_crtc = to_vc4_crtc(crtc);
        const struct vc4_pv_data *pv_data = vc4_crtc_to_vc4_pv_data(vc4_crtc);
-       struct drm_crtc_state *state = crtc->state;
-       struct drm_display_mode *mode = &state->adjusted_mode;
+       struct drm_crtc_state *crtc_state = crtc->state;
+       struct drm_display_mode *mode = &crtc_state->adjusted_mode;
        bool interlace = mode->flags & DRM_MODE_FLAG_INTERLACE;
        u32 pixel_rep = (mode->flags & DRM_MODE_FLAG_DBLCLK) ? 2 : 1;
        bool is_dsi = (vc4_encoder->type == VC4_ENCODER_TYPE_DSI0 ||
        if (vc4_encoder->pre_crtc_configure)
                vc4_encoder->pre_crtc_configure(encoder, state);
 
-       vc4_crtc_config_pv(crtc);
+       vc4_crtc_config_pv(crtc, state);
 
        CRTC_WRITE(PV_CONTROL, CRTC_READ(PV_CONTROL) | PV_CONTROL_EN);