drm/i915/xehp: CCS should use RCS setup functions

The compute engine handles the same commands the render engine can
(except 3D pipeline), so it makes sense that CCS is more similar to RCS
than non-render engines.

The CCS context state (lrc) is also similar to the render one, so reuse
it. Note that the compute engine has its own CTX_R_PWR_CLK_STATE
register.

In order to avoid having multiple RCS && CCS checks, add the following
engine flag:
 - I915_ENGINE_HAS_RCS_REG_STATE - use the render (larger) reg state ctx.

BSpec: 46260
Original-author: Michel Thierry
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>
Cc: Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>
Signed-off-by: Aravind Iddamsetty <aravind.iddamsetty@intel.com>
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Reviewed-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220301231549.1817978-6-matthew.d.roper@intel.com

diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
index bd60d42238fb00cb2feb7f87c0ad4d9af8c24433..7609db87df056f4cf674c84038a1f49292b0a892 100644 (file)
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_context.c
@@ -885,7 +885,9 @@ out_file:
        return err;
 }
 
-static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *vma)
+static int rpcs_query_batch(struct drm_i915_gem_object *rpcs,
+                           struct i915_vma *vma,
+                           struct intel_engine_cs *engine)
 {
        u32 *cmd;
 
@@ -896,7 +898,7 @@ static int rpcs_query_batch(struct drm_i915_gem_object *rpcs, struct i915_vma *v
                return PTR_ERR(cmd);
 
        *cmd++ = MI_STORE_REGISTER_MEM_GEN8;
-       *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(RENDER_RING_BASE));
+       *cmd++ = i915_mmio_reg_offset(GEN8_R_PWR_CLK_STATE(engine->mmio_base));
        *cmd++ = lower_32_bits(vma->node.start);
        *cmd++ = upper_32_bits(vma->node.start);
        *cmd = MI_BATCH_BUFFER_END;
@@ -957,7 +959,7 @@ retry:
        if (err)
                goto err_vma;
 
-       err = rpcs_query_batch(rpcs, vma);
+       err = rpcs_query_batch(rpcs, vma, ce->engine);
        if (err)
                goto err_batch;
 

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_cs.c b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
index 3150c0847f658be9f26a2809906e9357294fd35e..edba18c942cf8fd511d547ff650b84a3e3ee33ac 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_cs.c
+++ b/drivers/gpu/drm/i915/gt/intel_engine_cs.c
@@ -208,6 +208,8 @@ u32 intel_engine_context_size(struct intel_gt *gt, u8 class)
        BUILD_BUG_ON(I915_GTT_PAGE_SIZE != PAGE_SIZE);
 
        switch (class) {
+       case COMPUTE_CLASS:
+               fallthrough;
        case RENDER_CLASS:
                switch (GRAPHICS_VER(gt->i915)) {
                default:
@@ -431,6 +433,10 @@ static int intel_engine_setup(struct intel_gt *gt, enum intel_engine_id id,
        if (GRAPHICS_VER(i915) == 12 && engine->class == RENDER_CLASS)
                engine->props.preempt_timeout_ms = 0;
 
+       /* features common between engines sharing EUs */
+       if (engine->class == RENDER_CLASS || engine->class == COMPUTE_CLASS)
+               engine->flags |= I915_ENGINE_HAS_RCS_REG_STATE;
+
        engine->defaults = engine->props; /* never to change again */
 
        engine->context_size = intel_engine_context_size(gt, engine->class);

diff --git a/drivers/gpu/drm/i915/gt/intel_engine_types.h b/drivers/gpu/drm/i915/gt/intel_engine_types.h
index f4533ccafbaf12fbe0f5da733f9eca9224c45891..5fa5f21bbf2d304a89b8a20cfd6f1d3514ca845a 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_engine_types.h
+++ b/drivers/gpu/drm/i915/gt/intel_engine_types.h
@@ -524,6 +524,7 @@ struct intel_engine_cs {
 #define I915_ENGINE_HAS_RELATIVE_MMIO BIT(6)
 #define I915_ENGINE_REQUIRES_CMD_PARSER BIT(7)
 #define I915_ENGINE_WANT_FORCED_PREEMPTION BIT(8)
+#define I915_ENGINE_HAS_RCS_REG_STATE  BIT(9)
        unsigned int flags;
 
        /*

diff --git a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
index 961d795220a308f9304c269f79e2d8f0ec8fe8b4..47fca5ebfa7676d5e1c0b94385f201fb8f3c0cd0 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_execlists_submission.c
@@ -3480,7 +3480,7 @@ int intel_execlists_submission_setup(struct intel_engine_cs *engine)
        logical_ring_default_vfuncs(engine);
        logical_ring_default_irqs(engine);
 
-       if (engine->class == RENDER_CLASS)
+       if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
                rcs_submission_override(engine);
 
        lrc_init_wa_ctx(engine);

diff --git a/drivers/gpu/drm/i915/gt/intel_lrc.c b/drivers/gpu/drm/i915/gt/intel_lrc.c
index 004e1216e65470f05496366c756c49f8c91e48a0..d333400d29fe657a9b61c75afd4de495388d1a9e 100644 (file)
--- a/drivers/gpu/drm/i915/gt/intel_lrc.c
+++ b/drivers/gpu/drm/i915/gt/intel_lrc.c
@@ -623,7 +623,7 @@ static const u8 *reg_offsets(const struct intel_engine_cs *engine)
        GEM_BUG_ON(GRAPHICS_VER(engine->i915) >= 12 &&
                   !intel_engine_has_relative_mmio(engine));
 
-       if (engine->class == RENDER_CLASS) {
+       if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE) {
                if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 55))
                        return dg2_rcs_offsets;
                else if (GRAPHICS_VER_FULL(engine->i915) >= IP_VER(12, 50))
@@ -1619,7 +1619,7 @@ void lrc_init_wa_ctx(struct intel_engine_cs *engine)
        unsigned int i;
        int err;
 
-       if (engine->class != RENDER_CLASS)
+       if (!(engine->flags & I915_ENGINE_HAS_RCS_REG_STATE))
                return;
 
        switch (GRAPHICS_VER(engine->i915)) {

diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
index 810910e8042ea26631da90c96b83aeef46950265..a5c17bb4edfe0bf13c4f9ece3a2505aff3e76188 100644 (file)
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_submission.c
@@ -3776,7 +3776,7 @@ int intel_guc_submission_setup(struct intel_engine_cs *engine)
        guc_default_irqs(engine);
        guc_init_breadcrumbs(engine);
 
-       if (engine->class == RENDER_CLASS)
+       if (engine->flags & I915_ENGINE_HAS_RCS_REG_STATE)
                rcs_submission_override(engine);
 
        lrc_init_wa_ctx(engine);