tile: set ARCH_KMALLOC_MINALIGN

Architectures that handle DMA-non-coherent memory need to set
ARCH_KMALLOC_MINALIGN to make sure that kmalloc'ed buffer is DMA-safe:
the buffer doesn't share a cache with the others.

Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>

diff --git a/arch/tile/include/asm/cache.h b/arch/tile/include/asm/cache.h
index ee597147e5cdd018d7bb9996fc6351c99105d23a..869a14f4ceaef3c7eede9a9eecfa8adb576fe272 100644 (file)
--- a/arch/tile/include/asm/cache.h
+++ b/arch/tile/include/asm/cache.h
@@ -31,6 +31,14 @@
 #define L2_CACHE_BYTES         (1 << L2_CACHE_SHIFT)
 #define L2_CACHE_ALIGN(x)      (((x)+(L2_CACHE_BYTES-1)) & -L2_CACHE_BYTES)
 
+/*
+ * TILE-Gx is fully coherents so we don't need to define
+ * ARCH_KMALLOC_MINALIGN.
+ */
+#ifndef __tilegx__
+#define ARCH_KMALLOC_MINALIGN  L2_CACHE_BYTES
+#endif
+
 /* use the cache line size for the L2, which is where it counts */
 #define SMP_CACHE_BYTES_SHIFT  L2_CACHE_SHIFT
 #define SMP_CACHE_BYTES                L2_CACHE_BYTES