if (likely(mc) && mc->func->intr_mask) {
                u32 mask = nvkm_top_intr_mask(device, devidx);
                for (map = mc->func->intr; !mask && map->stat; map++) {
-                       if (map->unit == devidx)
+                       if (map->type + map->inst == devidx)
                                mask = map->stat;
                }
                mc->func->intr_mask(mc, mask, en ? mask : 0);
 
        for (map = mc->func->intr; map->stat; map++) {
                if (intr & map->stat) {
-                       subdev = nvkm_device_subdev(device, map->unit, 0);
+                       subdev = nvkm_device_subdev(device, map->type, map->inst);
                        if (subdev)
                                nvkm_subdev_intr(subdev);
                        stat &= ~map->stat;
                if (!(pmc_enable = nvkm_top_reset(device, devidx))) {
                        for (map = mc->func->reset; map && map->stat; map++) {
                                if (!isauto || !map->noauto) {
-                                       if (map->unit == devidx) {
+                                       if (map->type + map->inst == devidx) {
                                                pmc_enable = map->stat;
                                                break;
                                        }
 
 gf100_mc_reset[] = {
        { 0x00020000, NVKM_ENGINE_MSPDEC },
        { 0x00008000, NVKM_ENGINE_MSVLD },
-       { 0x00002000, NVKM_SUBDEV_PMU, true },
+       { 0x00002000, NVKM_SUBDEV_PMU, 0, true },
        { 0x00001000, NVKM_ENGINE_GR },
        { 0x00000100, NVKM_ENGINE_FIFO },
-       { 0x00000080, NVKM_ENGINE_CE1 },
-       { 0x00000040, NVKM_ENGINE_CE0 },
+       { 0x00000080, NVKM_ENGINE_CE, 1 },
+       { 0x00000040, NVKM_ENGINE_CE, 0 },
        { 0x00000002, NVKM_ENGINE_MSPPP },
        {}
 };
        { 0x00008000, NVKM_ENGINE_MSVLD },
        { 0x00001000, NVKM_ENGINE_GR },
        { 0x00000100, NVKM_ENGINE_FIFO },
-       { 0x00000040, NVKM_ENGINE_CE1 },
-       { 0x00000020, NVKM_ENGINE_CE0 },
+       { 0x00000040, NVKM_ENGINE_CE, 1 },
+       { 0x00000020, NVKM_ENGINE_CE, 0 },
        { 0x00000001, NVKM_ENGINE_MSPPP },
        { 0x40000000, NVKM_SUBDEV_IBUS },
        { 0x10000000, NVKM_SUBDEV_BUS },
 
 const struct nvkm_mc_map
 gk104_mc_reset[] = {
        { 0x00000100, NVKM_ENGINE_FIFO },
-       { 0x00002000, NVKM_SUBDEV_PMU, true },
+       { 0x00002000, NVKM_SUBDEV_PMU, 0, true },
        {}
 };
 
 
 gt215_mc_reset[] = {
        { 0x04008000, NVKM_ENGINE_MSVLD },
        { 0x01020000, NVKM_ENGINE_MSPDEC },
-       { 0x00802000, NVKM_ENGINE_CE0 },
+       { 0x00802000, NVKM_ENGINE_CE, 0 },
        { 0x00400002, NVKM_ENGINE_MSPPP },
        { 0x00201000, NVKM_ENGINE_GR },
        { 0x00000100, NVKM_ENGINE_FIFO },
 static const struct nvkm_mc_map
 gt215_mc_intr[] = {
        { 0x04000000, NVKM_ENGINE_DISP },
-       { 0x00400000, NVKM_ENGINE_CE0 },
+       { 0x00400000, NVKM_ENGINE_CE, 0 },
        { 0x00020000, NVKM_ENGINE_MSPDEC },
        { 0x00008000, NVKM_ENGINE_MSVLD },
        { 0x00001000, NVKM_ENGINE_GR },
 
 
 struct nvkm_mc_map {
        u32 stat;
-       u32 unit;
+       enum nvkm_subdev_type type;
+       int inst;
        bool noauto;
 };