#define FLEXCAN_QUIRK_NR_IRQ_3 BIT(12)
 /* Setup 16 mailboxes */
 #define FLEXCAN_QUIRK_NR_MB_16 BIT(13)
+/* Device supports RX via mailboxes */
+#define FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX BIT(14)
+/* Device supports RTR reception via mailboxes */
+#define FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR BIT(15)
+/* Device supports RX via FIFO */
+#define FLEXCAN_QUIRK_SUPPPORT_RX_FIFO BIT(16)
 
 /* Structure of the message buffer */
 struct flexcan_mb {
 
 static const struct flexcan_devtype_data fsl_mcf5441x_devtype_data = {
        .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
-               FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16,
+               FLEXCAN_QUIRK_NR_IRQ_3 | FLEXCAN_QUIRK_NR_MB_16 |
+               FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
 };
 
 static const struct flexcan_devtype_data fsl_p1010_devtype_data = {
        .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
                FLEXCAN_QUIRK_BROKEN_PERR_STATE |
-               FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN,
+               FLEXCAN_QUIRK_DEFAULT_BIG_ENDIAN |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
 };
 
 static const struct flexcan_devtype_data fsl_imx25_devtype_data = {
        .quirks = FLEXCAN_QUIRK_BROKEN_WERR_STATE |
-               FLEXCAN_QUIRK_BROKEN_PERR_STATE,
+               FLEXCAN_QUIRK_BROKEN_PERR_STATE |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
 };
 
 static const struct flexcan_devtype_data fsl_imx28_devtype_data = {
-       .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE,
+       .quirks = FLEXCAN_QUIRK_BROKEN_PERR_STATE |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_FIFO,
 };
 
 static const struct flexcan_devtype_data fsl_imx6q_devtype_data = {
        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
                FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
-               FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR,
+               FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 };
 
 static const struct flexcan_devtype_data fsl_imx8qm_devtype_data = {
        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
                FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
-               FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW,
+               FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SETUP_STOP_MODE_SCFW |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 };
 
 static struct flexcan_devtype_data fsl_imx8mp_devtype_data = {
        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
                FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
                FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SETUP_STOP_MODE_GPR |
-               FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC,
+               FLEXCAN_QUIRK_SUPPORT_FD | FLEXCAN_QUIRK_SUPPORT_ECC |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 };
 
 static const struct flexcan_devtype_data fsl_vf610_devtype_data = {
        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
                FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_USE_RX_MAILBOX |
-               FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC,
+               FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_SUPPORT_ECC |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 };
 
 static const struct flexcan_devtype_data fsl_ls1021a_r2_devtype_data = {
        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
-               FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX,
+               FLEXCAN_QUIRK_BROKEN_PERR_STATE | FLEXCAN_QUIRK_USE_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 };
 
 static const struct flexcan_devtype_data fsl_lx2160a_r1_devtype_data = {
        .quirks = FLEXCAN_QUIRK_DISABLE_RXFG | FLEXCAN_QUIRK_ENABLE_EACEN_RRS |
                FLEXCAN_QUIRK_DISABLE_MECR | FLEXCAN_QUIRK_BROKEN_PERR_STATE |
                FLEXCAN_QUIRK_USE_RX_MAILBOX | FLEXCAN_QUIRK_SUPPORT_FD |
-               FLEXCAN_QUIRK_SUPPORT_ECC,
+               FLEXCAN_QUIRK_SUPPORT_ECC |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR,
 };
 
 static const struct can_bittiming_const flexcan_bittiming_const = {
                return -ENODEV;
 
        if ((devtype_data->quirks & FLEXCAN_QUIRK_SUPPORT_FD) &&
-           !(devtype_data->quirks & FLEXCAN_QUIRK_USE_RX_MAILBOX)) {
-               dev_err(&pdev->dev, "CAN-FD mode doesn't work with FIFO mode!\n");
+           !((devtype_data->quirks &
+              (FLEXCAN_QUIRK_USE_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+               FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR |
+               FLEXCAN_QUIRK_SUPPPORT_RX_FIFO)) ==
+             (FLEXCAN_QUIRK_USE_RX_MAILBOX |
+              FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+              FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR))) {
+               dev_err(&pdev->dev, "CAN-FD mode doesn't work in RX-FIFO mode!\n");
+               return -EINVAL;
+       }
+
+       if ((devtype_data->quirks &
+            (FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX |
+             FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR)) ==
+           FLEXCAN_QUIRK_SUPPPORT_RX_MAILBOX_RTR) {
+               dev_err(&pdev->dev,
+                       "Quirks (0x%08x) inconsistent: RX_MAILBOX_RX supported but not RX_MAILBOX\n",
+                       devtype_data->quirks);
                return -EINVAL;
        }