drm/amd/display: fix segfault on insufficient TG during validation

Signed-off-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Reviewed-by: Dmytro Laktyushkin <Dmytro.Laktyushkin@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
index 8d7bc1fa9ffe7327c2a69fcd1e48bea0b87d2066..d7a92eca8a273f33de950f0331378847c41ba512 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
+++ b/drivers/gpu/drm/amd/display/dc/core/dc_resource.c
@@ -1700,7 +1700,7 @@ enum dc_status resource_map_pool_resources(
                pipe_idx = acquire_first_split_pipe(&context->res_ctx, pool, stream);
 #endif
 
-       if (pipe_idx < 0)
+       if (pipe_idx < 0 || context->res_ctx.pipe_ctx[pipe_idx].stream_res.tg == NULL)
                return DC_NO_CONTROLLER_RESOURCE;
 
        pipe_ctx = &context->res_ctx.pipe_ctx[pipe_idx];