uint64_t                        gpu_addr;
        uint32_t                        *ptr;
        struct amdgpu_user_fence        *user;
-       struct amdgpu_vm                *vm;
        unsigned                        vm_id;
        uint64_t                        vm_pd_addr;
        struct amdgpu_ctx               *ctx;
 extern const struct amd_sched_backend_ops amdgpu_sched_ops;
 
 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-                    struct amdgpu_job **job);
+                    struct amdgpu_job **job, struct amdgpu_vm *vm);
 int amdgpu_job_alloc_with_ib(struct amdgpu_device *adev, unsigned size,
                             struct amdgpu_job **job);
 
 void amdgpu_ib_free(struct amdgpu_device *adev, struct amdgpu_ib *ib, struct fence *f);
 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                       struct amdgpu_ib *ib, struct fence *last_vm_update,
-                      struct fence **f);
+                      struct amdgpu_job *job, struct fence **f);
 int amdgpu_ib_pool_init(struct amdgpu_device *adev);
 void amdgpu_ib_pool_fini(struct amdgpu_device *adev);
 int amdgpu_ib_ring_tests(struct amdgpu_device *adev);
 struct amdgpu_job {
        struct amd_sched_job    base;
        struct amdgpu_device    *adev;
+       struct amdgpu_vm        *vm;
        struct amdgpu_ring      *ring;
        struct amdgpu_sync      sync;
        struct amdgpu_ib        *ibs;
 
 int amdgpu_cs_parser_init(struct amdgpu_cs_parser *p, void *data)
 {
        struct amdgpu_fpriv *fpriv = p->filp->driver_priv;
+       struct amdgpu_vm *vm = &fpriv->vm;
        union drm_amdgpu_cs *cs = data;
        uint64_t *chunk_array_user;
        uint64_t *chunk_array;
                }
        }
 
-       ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job);
+       ret = amdgpu_job_alloc(p->adev, num_ibs, &p->job, vm);
        if (ret)
                goto free_all_kdata;
 
 
                        ib->gpu_addr = amdgpu_sa_bo_gpu_addr(ib->sa_bo);
        }
 
-       ib->vm = vm;
        ib->vm_id = 0;
 
        return 0;
  */
 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                       struct amdgpu_ib *ibs, struct fence *last_vm_update,
-                      struct fence **f)
+                      struct amdgpu_job *job, struct fence **f)
 {
        struct amdgpu_device *adev = ring->adev;
        struct amdgpu_ib *ib = &ibs[0];
        struct amdgpu_ctx *ctx, *old_ctx;
-       struct amdgpu_vm *vm;
        struct fence *hwf;
+       struct amdgpu_vm *vm = NULL;
        unsigned i, patch_offset = ~0;
 
        int r = 0;
                return -EINVAL;
 
        ctx = ibs->ctx;
-       vm = ibs->vm;
+       if (job) /* for domain0 job like ring test, ibs->job is not assigned */
+               vm = job->vm;
 
        if (!ring->ready) {
                dev_err(adev->dev, "couldn't schedule ib\n");
        old_ctx = ring->current_ctx;
        for (i = 0; i < num_ibs; ++i) {
                ib = &ibs[i];
-
-               if (ib->ctx != ctx || ib->vm != vm) {
-                       ring->current_ctx = old_ctx;
-                       if (ib->vm_id)
-                               amdgpu_vm_reset_id(adev, ib->vm_id);
-                       amdgpu_ring_undo(ring);
-                       return -EINVAL;
-               }
                amdgpu_ring_emit_ib(ring, ib);
                ring->current_ctx = ctx;
        }
 
 }
 
 int amdgpu_job_alloc(struct amdgpu_device *adev, unsigned num_ibs,
-                    struct amdgpu_job **job)
+                    struct amdgpu_job **job, struct amdgpu_vm *vm)
 {
        size_t size = sizeof(struct amdgpu_job);
 
                return -ENOMEM;
 
        (*job)->adev = adev;
+       (*job)->vm = vm;
        (*job)->ibs = (void *)&(*job)[1];
        (*job)->num_ibs = num_ibs;
        INIT_WORK(&(*job)->base.work_free_job, amdgpu_job_free_handler);
 {
        int r;
 
-       r = amdgpu_job_alloc(adev, 1, job);
+       r = amdgpu_job_alloc(adev, 1, job, NULL);
        if (r)
                return r;
 
 static struct fence *amdgpu_job_dependency(struct amd_sched_job *sched_job)
 {
        struct amdgpu_job *job = to_amdgpu_job(sched_job);
-       struct amdgpu_vm *vm = job->ibs->vm;
+       struct amdgpu_vm *vm = job->vm;
 
        struct fence *fence = amdgpu_sync_get_fence(&job->sync);
 
 
        trace_amdgpu_sched_run_job(job);
        r = amdgpu_ib_schedule(job->ring, job->num_ibs, job->ibs,
-                              job->sync.last_vm_update, &fence);
+                              job->sync.last_vm_update, job, &fence);
        if (r) {
                DRM_ERROR("Error scheduling IBs (%d)\n", r);
                goto err;
 
        ib->length_dw = 16;
 
        if (direct) {
-               r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+               r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
                job->fence = f;
                if (r)
                        goto err_free;
 
        for (i = ib->length_dw; i < ib_size_dw; ++i)
                ib->ptr[i] = 0x0;
 
-       r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+       r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
        job->fence = f;
        if (r)
                goto err;
                ib->ptr[i] = 0x0;
 
        if (direct) {
-               r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
+               r = amdgpu_ib_schedule(ring, 1, ib, NULL, NULL, &f);
                job->fence = f;
                if (r)
                        goto err;
 
            pd_addr != AMDGPU_VM_NO_FLUSH || gds_switch_needed))
                amdgpu_ring_emit_pipeline_sync(ring);
 
-       if (pd_addr != AMDGPU_VM_NO_FLUSH) {
+       if (ring->funcs->emit_vm_flush &&
+           pd_addr != AMDGPU_VM_NO_FLUSH) {
                struct fence *fence;
 
                trace_amdgpu_vm_flush(pd_addr, ring->idx, vm_id);
 
        ib.ptr[3] = 1;
        ib.ptr[4] = 0xDEADBEEF;
        ib.length_dw = 5;
-       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
        if (r)
                goto err1;
 
 
        ib.ptr[2] = 0xDEADBEEF;
        ib.length_dw = 3;
 
-       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
        if (r)
                goto err2;
 
 
        ib.ptr[2] = 0xDEADBEEF;
        ib.length_dw = 3;
 
-       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
        if (r)
                goto err2;
 
        ib.ptr[ib.length_dw++] = EVENT_TYPE(7) | EVENT_INDEX(4);
 
        /* shedule the ib on the ring */
-       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
        if (r) {
                DRM_ERROR("amdgpu: ib submit failed (%d).\n", r);
                goto fail;
 
        ib.ptr[7] = SDMA_PKT_HEADER_OP(SDMA_OP_NOP);
        ib.length_dw = 8;
 
-       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
        if (r)
                goto err1;
 
 
        ib.ptr[7] = SDMA_PKT_NOP_HEADER_OP(SDMA_OP_NOP);
        ib.length_dw = 8;
 
-       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, &f);
+       r = amdgpu_ib_schedule(ring, 1, &ib, NULL, NULL, &f);
        if (r)
                goto err1;