drm/amd/display: Reduce frame size in the bouding box for DCN20

GCC throw warnings for the function dcn20_update_bounding_box due to its
frame size that looks like this:

 error: the frame size of 1936 bytes is larger than 1024 bytes [-Werror=frame-larger-than=]

This commit fixes this issue by eliminating an intermediary variable
that creates a large array.

Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Hamza Mahfooz <hamza.mahfooz@amd.com>
Cc: Aurabindo Pillai <aurabindo.pillai@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
index eeec40f6fd0aa3882941d4545558cdc2b04df069..d9cc178f6980efd289a0d3b7cea16a78ef45e409 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
+++ b/drivers/gpu/drm/amd/display/dc/dml/dcn20/dcn20_fpu.c
@@ -1456,21 +1456,20 @@ void dcn20_calculate_wm(
 void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_st *bb,
                struct pp_smu_nv_clock_table *max_clocks, unsigned int *uclk_states, unsigned int num_states)
 {
-       struct _vcs_dpi_voltage_scaling_st calculated_states[DC__VOLTAGE_STATES];
-       int i;
        int num_calculated_states = 0;
        int min_dcfclk = 0;
+       int i;
 
        dc_assert_fp_enabled();
 
        if (num_states == 0)
                return;
 
-       memset(calculated_states, 0, sizeof(calculated_states));
+       memset(bb->clock_limits, 0, sizeof(bb->clock_limits));
 
-       if (dc->bb_overrides.min_dcfclk_mhz > 0)
+       if (dc->bb_overrides.min_dcfclk_mhz > 0) {
                min_dcfclk = dc->bb_overrides.min_dcfclk_mhz;
-       else {
+       } else {
                if (ASICREV_IS_NAVI12_P(dc->ctx->asic_id.hw_internal_rev))
                        min_dcfclk = 310;
                else
@@ -1481,36 +1480,35 @@ void dcn20_update_bounding_box(struct dc *dc, struct _vcs_dpi_soc_bounding_box_s
 
        for (i = 0; i < num_states; i++) {
                int min_fclk_required_by_uclk;
-               calculated_states[i].state = i;
-               calculated_states[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
+               bb->clock_limits[i].state = i;
+               bb->clock_limits[i].dram_speed_mts = uclk_states[i] * 16 / 1000;
 
                // FCLK:UCLK ratio is 1.08
                min_fclk_required_by_uclk = div_u64(((unsigned long long)uclk_states[i]) * 1080,
                        1000000);
 
-               calculated_states[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
+               bb->clock_limits[i].fabricclk_mhz = (min_fclk_required_by_uclk < min_dcfclk) ?
                                min_dcfclk : min_fclk_required_by_uclk;
 
-               calculated_states[i].socclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
-                               max_clocks->socClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
+               bb->clock_limits[i].socclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->socClockInKhz / 1000) ?
+                               max_clocks->socClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
 
-               calculated_states[i].dcfclk_mhz = (calculated_states[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
-                               max_clocks->dcfClockInKhz / 1000 : calculated_states[i].fabricclk_mhz;
+               bb->clock_limits[i].dcfclk_mhz = (bb->clock_limits[i].fabricclk_mhz > max_clocks->dcfClockInKhz / 1000) ?
+                               max_clocks->dcfClockInKhz / 1000 : bb->clock_limits[i].fabricclk_mhz;
 
-               calculated_states[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
-               calculated_states[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
-               calculated_states[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
+               bb->clock_limits[i].dispclk_mhz = max_clocks->displayClockInKhz / 1000;
+               bb->clock_limits[i].dppclk_mhz = max_clocks->displayClockInKhz / 1000;
+               bb->clock_limits[i].dscclk_mhz = max_clocks->displayClockInKhz / (1000 * 3);
 
-               calculated_states[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
+               bb->clock_limits[i].phyclk_mhz = max_clocks->phyClockInKhz / 1000;
 
                num_calculated_states++;
        }
 
-       calculated_states[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
-       calculated_states[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
-       calculated_states[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
+       bb->clock_limits[num_calculated_states - 1].socclk_mhz = max_clocks->socClockInKhz / 1000;
+       bb->clock_limits[num_calculated_states - 1].fabricclk_mhz = max_clocks->socClockInKhz / 1000;
+       bb->clock_limits[num_calculated_states - 1].dcfclk_mhz = max_clocks->dcfClockInKhz / 1000;
 
-       memcpy(bb->clock_limits, calculated_states, sizeof(bb->clock_limits));
        bb->num_states = num_calculated_states;
 
        // Duplicate the last state, DML always an extra state identical to max state to work