drm/i915: Mask everything in ring HWSTAM on gen6+ in ringbuffer mode

The execlist code already masks everything in the ring HWSTAM, but
the ringbuffer code doesn't. Let's go ahead and do that. Pre-gen6
platforms setup HWSTAM during irq setup already since there's just
the one register, and it also contains bits for non-ring interrupts.

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20170818183705.27850-13-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.c b/drivers/gpu/drm/i915/intel_ringbuffer.c
index 8af8871a8594f067d8798917f6ec932f0c5f66d2..22e5ea8516b66a4e81eb379b1601e4b1db0a6f8a 100644 (file)
--- a/drivers/gpu/drm/i915/intel_ringbuffer.c
+++ b/drivers/gpu/drm/i915/intel_ringbuffer.c
@@ -428,6 +428,9 @@ static void intel_ring_setup_status_page(struct intel_engine_cs *engine)
                mmio = RING_HWS_PGA(engine->mmio_base);
        }
 
+       if (INTEL_GEN(dev_priv) >= 6)
+               I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff);
+
        I915_WRITE(mmio, engine->status_page.ggtt_offset);
        POSTING_READ(mmio);