bitmap_zero(used_mask, X86_PMC_IDX_MAX);
 
+       if (x86_pmu.start_scheduling)
+               x86_pmu.start_scheduling(cpuc);
+
        for (i = 0, wmin = X86_PMC_IDX_MAX, wmax = 0; i < n; i++) {
                hwc = &cpuc->event_list[i]->hw;
                c = x86_pmu.get_event_constraints(cpuc, cpuc->event_list[i]);
                for (i = 0; i < n; i++) {
                        e = cpuc->event_list[i];
                        e->hw.flags |= PERF_X86_EVENT_COMMITTED;
+                       if (x86_pmu.commit_scheduling)
+                               x86_pmu.commit_scheduling(cpuc, e, assign[i]);
                }
        }
        /*
                                x86_pmu.put_event_constraints(cpuc, e);
                }
        }
+
+       if (x86_pmu.stop_scheduling)
+               x86_pmu.stop_scheduling(cpuc);
+
        return num ? -EINVAL : 0;
 }
 
 
 
        void            (*put_event_constraints)(struct cpu_hw_events *cpuc,
                                                 struct perf_event *event);
+
+       void            (*commit_scheduling)(struct cpu_hw_events *cpuc,
+                                            struct perf_event *event,
+                                            int cntr);
+
+       void            (*start_scheduling)(struct cpu_hw_events *cpuc);
+
+       void            (*stop_scheduling)(struct cpu_hw_events *cpuc);
+
        struct event_constraint *event_constraints;
        struct x86_pmu_quirk *quirks;
        int             perfctr_second_write;