drm/amd/amdgpu: Avoid writing GMC registers under sriov in gmc9

[Why]
For Vega10, disabling gart of gfxhub could mess up KIQ and PSP
under sriov mode, and lead to DMAR on host side.

[How]
Skip writing GMC registers under sriov.

Signed-off-by: YuBiao Wang <YuBiao.Wang@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
index bda1542ef1ddfe6149fd7bcf51d77827ab1e4a0c..480e41847d7c0b199b1cbf30f6f7c9978dd26bc0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.c
@@ -348,6 +348,10 @@ static void gfxhub_v1_0_gart_disable(struct amdgpu_device *adev)
                WREG32_SOC15_OFFSET(GC, 0, mmVM_CONTEXT0_CNTL,
                                    i * hub->ctx_distance, 0);
 
+       if (amdgpu_sriov_vf(adev))
+               /* Avoid write to GMC registers */
+               return;
+
        /* Setup TLB control */
        tmp = RREG32_SOC15(GC, 0, mmMC_VM_MX_L1_TLB_CNTL);
        tmp = REG_SET_FIELD(tmp, MC_VM_MX_L1_TLB_CNTL, ENABLE_L1_TLB, 0);