drm/amdgpu: rename vm_id to vmid

sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.c
sed -i "s/vm_id/vmid/g" drivers/gpu/drm/amd/amdgpu/*.h

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu.h b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
index bbe06e04dcb65f1936096b734a55e2423bf71f00..642bea2c9b3a171cc54ddcd3f10ba1f2f052f93d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu.h
@@ -351,7 +351,7 @@ struct amdgpu_gart_funcs {
        /* get the pde for a given mc addr */
        void (*get_vm_pde)(struct amdgpu_device *adev, int level,
                           u64 *dst, u64 *flags);
-       uint32_t (*get_invalidate_req)(unsigned int vm_id);
+       uint32_t (*get_invalidate_req)(unsigned int vmid);
 };
 
 /* provided by the ih block */
@@ -1124,7 +1124,7 @@ struct amdgpu_job {
        void                    *owner;
        uint64_t                fence_ctx; /* the fence_context this job uses */
        bool                    vm_needs_flush;
-       unsigned                vm_id;
+       unsigned                vmid;
        uint64_t                vm_pd_addr;
        uint32_t                gds_base, gds_size;
        uint32_t                gws_base, gws_size;
@@ -1849,7 +1849,7 @@ amdgpu_get_sdma_instance(struct amdgpu_ring *ring)
 #define amdgpu_ring_get_rptr(r) (r)->funcs->get_rptr((r))
 #define amdgpu_ring_get_wptr(r) (r)->funcs->get_wptr((r))
 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
-#define amdgpu_ring_emit_ib(r, ib, vm_id, c) (r)->funcs->emit_ib((r), (ib), (vm_id), (c))
+#define amdgpu_ring_emit_ib(r, ib, vmid, c) (r)->funcs->emit_ib((r), (ib), (vmid), (c))
 #define amdgpu_ring_emit_pipeline_sync(r) (r)->funcs->emit_pipeline_sync((r))
 #define amdgpu_ring_emit_vm_flush(r, vmid, addr) (r)->funcs->emit_vm_flush((r), (vmid), (addr))
 #define amdgpu_ring_emit_fence(r, addr, seq, flags) (r)->funcs->emit_fence((r), (addr), (seq), (flags))

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
index 03a69942cce50e020ecd101f410310ab36271ea2..a162d87ca0c8e7bedf2d936f4cd63abf98fe534e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ib.c
@@ -149,7 +149,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                return -EINVAL;
        }
 
-       if (vm && !job->vm_id) {
+       if (vm && !job->vmid) {
                dev_err(adev->dev, "VM IB without ID\n");
                return -EINVAL;
        }
@@ -211,7 +211,7 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
                        !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
                        continue;
 
-               amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0,
+               amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0,
                                    need_ctx_switch);
                need_ctx_switch = false;
        }
@@ -229,8 +229,8 @@ int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs,
        r = amdgpu_fence_emit(ring, f);
        if (r) {
                dev_err(adev->dev, "failed to emit fence (%d)\n", r);
-               if (job && job->vm_id)
-                       amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vm_id);
+               if (job && job->vmid)
+                       amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
                amdgpu_ring_undo(ring);
                return r;
        }

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
index 71f8a76d4c10ec6bf24cdca0b52b56ad6b250008..d24884b419cb3fc637766ca76f287d1953d08a4d 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ids.c
@@ -150,7 +150,7 @@ static int amdgpu_vmid_grab_reserved_locked(struct amdgpu_vm *vm,
                dma_fence_put(id->last_flush);
                id->last_flush = NULL;
        }
-       job->vm_id = id - id_mgr->ids;
+       job->vmid = id - id_mgr->ids;
        trace_amdgpu_vm_grab_id(vm, ring, job);
 out:
        return r;
@@ -301,7 +301,7 @@ needs_flush:
 no_flush_needed:
        list_move_tail(&id->list, &id_mgr->ids_lru);
 
-       job->vm_id = id - id_mgr->ids;
+       job->vmid = id - id_mgr->ids;
        trace_amdgpu_vm_grab_id(vm, ring, job);
 
 error:
@@ -360,7 +360,7 @@ void amdgpu_vmid_free_reserved(struct amdgpu_device *adev,
  * amdgpu_vmid_reset - reset VMID to zero
  *
  * @adev: amdgpu device structure
- * @vm_id: vmid number to use
+ * @vmid: vmid number to use
  *
  * Reset saved GDW, GWS and OA to force switch on next flush.
  */

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index ada89358e2207b566004495053b00e3ba68530b8..29cf10927a92ce6655064c9b028644473e69182b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -105,8 +105,8 @@ struct amdgpu_iv_entry {
        unsigned client_id;
        unsigned src_id;
        unsigned ring_id;
-       unsigned vm_id;
-       unsigned vm_id_src;
+       unsigned vmid;
+       unsigned vmid_src;
        uint64_t timestamp;
        unsigned timestamp_src;
        unsigned pas_id;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
index cdc9e0f5336a9e8f9ff48b3e7f782eddcda98165..2bd56760c7441fdc720d3a469fef424ae39741ea 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_job.c
@@ -158,7 +158,7 @@ static struct dma_fence *amdgpu_job_dependency(struct drm_sched_job *sched_job,
                }
        }
 
-       while (fence == NULL && vm && !job->vm_id) {
+       while (fence == NULL && vm && !job->vmid) {
                struct amdgpu_ring *ring = job->ring;
 
                r = amdgpu_vmid_grab(vm, ring, &job->sync,

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
index 010f69084af5971417d94ba6a5b817d7aa9c98bf..102dad3edf6a44be8462ea1d9303ad0be2fdd68b 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
@@ -121,11 +121,11 @@ struct amdgpu_ring_funcs {
        /* command emit functions */
        void (*emit_ib)(struct amdgpu_ring *ring,
                        struct amdgpu_ib *ib,
-                       unsigned vm_id, bool ctx_switch);
+                       unsigned vmid, bool ctx_switch);
        void (*emit_fence)(struct amdgpu_ring *ring, uint64_t addr,
                           uint64_t seq, unsigned flags);
        void (*emit_pipeline_sync)(struct amdgpu_ring *ring);
-       void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vm_id,
+       void (*emit_vm_flush)(struct amdgpu_ring *ring, unsigned vmid,
                              uint64_t pd_addr);
        void (*emit_hdp_flush)(struct amdgpu_ring *ring);
        void (*emit_hdp_invalidate)(struct amdgpu_ring *ring);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
index 06525f2c36c3cd2cfc670f1713f0778f62cbbf5e..cace7a93fc943beab80622d98a2ba5a01ec71884 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_trace.h
@@ -82,8 +82,8 @@ TRACE_EVENT(amdgpu_iv,
                             __field(unsigned, client_id)
                             __field(unsigned, src_id)
                             __field(unsigned, ring_id)
-                            __field(unsigned, vm_id)
-                            __field(unsigned, vm_id_src)
+                            __field(unsigned, vmid)
+                            __field(unsigned, vmid_src)
                             __field(uint64_t, timestamp)
                             __field(unsigned, timestamp_src)
                             __field(unsigned, pas_id)
@@ -93,8 +93,8 @@ TRACE_EVENT(amdgpu_iv,
                           __entry->client_id = iv->client_id;
                           __entry->src_id = iv->src_id;
                           __entry->ring_id = iv->ring_id;
-                          __entry->vm_id = iv->vm_id;
-                          __entry->vm_id_src = iv->vm_id_src;
+                          __entry->vmid = iv->vmid;
+                          __entry->vmid_src = iv->vmid_src;
                           __entry->timestamp = iv->timestamp;
                           __entry->timestamp_src = iv->timestamp_src;
                           __entry->pas_id = iv->pas_id;
@@ -103,9 +103,9 @@ TRACE_EVENT(amdgpu_iv,
                           __entry->src_data[2] = iv->src_data[2];
                           __entry->src_data[3] = iv->src_data[3];
                           ),
-           TP_printk("client_id:%u src_id:%u ring:%u vm_id:%u timestamp: %llu pas_id:%u src_data: %08x %08x %08x %08x\n",
+           TP_printk("client_id:%u src_id:%u ring:%u vmid:%u timestamp: %llu pas_id:%u src_data: %08x %08x %08x %08x\n",
                      __entry->client_id, __entry->src_id,
-                     __entry->ring_id, __entry->vm_id,
+                     __entry->ring_id, __entry->vmid,
                      __entry->timestamp, __entry->pas_id,
                      __entry->src_data[0], __entry->src_data[1],
                      __entry->src_data[2], __entry->src_data[3])
@@ -219,7 +219,7 @@ TRACE_EVENT(amdgpu_vm_grab_id,
            TP_STRUCT__entry(
                             __field(struct amdgpu_vm *, vm)
                             __field(u32, ring)
-                            __field(u32, vm_id)
+                            __field(u32, vmid)
                             __field(u32, vm_hub)
                             __field(u64, pd_addr)
                             __field(u32, needs_flush)
@@ -228,13 +228,13 @@ TRACE_EVENT(amdgpu_vm_grab_id,
            TP_fast_assign(
                           __entry->vm = vm;
                           __entry->ring = ring->idx;
-                          __entry->vm_id = job->vm_id;
+                          __entry->vmid = job->vmid;
                           __entry->vm_hub = ring->funcs->vmhub,
                           __entry->pd_addr = job->vm_pd_addr;
                           __entry->needs_flush = job->vm_needs_flush;
                           ),
            TP_printk("vm=%p, ring=%u, id=%u, hub=%u, pd_addr=%010Lx needs_flush=%u",
-                     __entry->vm, __entry->ring, __entry->vm_id,
+                     __entry->vm, __entry->ring, __entry->vmid,
                      __entry->vm_hub, __entry->pd_addr, __entry->needs_flush)
 );
 
@@ -357,24 +357,24 @@ TRACE_EVENT(amdgpu_vm_copy_ptes,
 );
 
 TRACE_EVENT(amdgpu_vm_flush,
-           TP_PROTO(struct amdgpu_ring *ring, unsigned vm_id,
+           TP_PROTO(struct amdgpu_ring *ring, unsigned vmid,
                     uint64_t pd_addr),
-           TP_ARGS(ring, vm_id, pd_addr),
+           TP_ARGS(ring, vmid, pd_addr),
            TP_STRUCT__entry(
                             __field(u32, ring)
-                            __field(u32, vm_id)
+                            __field(u32, vmid)
                             __field(u32, vm_hub)
                             __field(u64, pd_addr)
                             ),
 
            TP_fast_assign(
                           __entry->ring = ring->idx;
-                          __entry->vm_id = vm_id;
+                          __entry->vmid = vmid;
                           __entry->vm_hub = ring->funcs->vmhub;
                           __entry->pd_addr = pd_addr;
                           ),
            TP_printk("ring=%u, id=%u, hub=%u, pd_addr=%010Lx",
-                     __entry->ring, __entry->vm_id,
+                     __entry->ring, __entry->vmid,
                      __entry->vm_hub,__entry->pd_addr)
 );
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
index 9857d482c94231302006d787f778ea0a265058fe..55a726a322e3e40d1c8289e47e70c6a5d76f9fa9 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.c
@@ -991,7 +991,7 @@ out:
  *
  */
 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
-                            unsigned vm_id, bool ctx_switch)
+                            unsigned vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, VCE_CMD_IB);
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
index 162cae94e3b1444ac572d7fee704970ade81e337..0fd378ae92c3faee3efd8d2f45a7561afecb8274 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vce.h
@@ -63,7 +63,7 @@ void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp);
 int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx);
 void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_ib *ib,
-                            unsigned vm_id, bool ctx_switch);
+                            unsigned vmid, bool ctx_switch);
 void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq,
                                unsigned flags);
 int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
index 01ee8e2258c84f25da07c8c46e79328743b2432d..946bc21c6d7d0624d0ced3c320d31269c07ee2d8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_vm.c
@@ -446,9 +446,9 @@ bool amdgpu_vm_need_pipeline_sync(struct amdgpu_ring *ring,
        bool gds_switch_needed;
        bool vm_flush_needed = job->vm_needs_flush || ring->has_compute_vm_bug;
 
-       if (job->vm_id == 0)
+       if (job->vmid == 0)
                return false;
-       id = &id_mgr->ids[job->vm_id];
+       id = &id_mgr->ids[job->vmid];
        gds_switch_needed = ring->funcs->emit_gds_switch && (
                id->gds_base != job->gds_base ||
                id->gds_size != job->gds_size ||
@@ -472,7 +472,7 @@ static bool amdgpu_vm_is_large_bar(struct amdgpu_device *adev)
  * amdgpu_vm_flush - hardware flush the vm
  *
  * @ring: ring to use for flush
- * @vm_id: vmid number to use
+ * @vmid: vmid number to use
  * @pd_addr: address of the page directory
  *
  * Emit a VM flush when it is necessary.
@@ -482,7 +482,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
        struct amdgpu_device *adev = ring->adev;
        unsigned vmhub = ring->funcs->vmhub;
        struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
-       struct amdgpu_vmid *id = &id_mgr->ids[job->vm_id];
+       struct amdgpu_vmid *id = &id_mgr->ids[job->vmid];
        bool gds_switch_needed = ring->funcs->emit_gds_switch && (
                id->gds_base != job->gds_base ||
                id->gds_size != job->gds_size ||
@@ -511,8 +511,8 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
        if (ring->funcs->emit_vm_flush && vm_flush_needed) {
                struct dma_fence *fence;
 
-               trace_amdgpu_vm_flush(ring, job->vm_id, job->vm_pd_addr);
-               amdgpu_ring_emit_vm_flush(ring, job->vm_id, job->vm_pd_addr);
+               trace_amdgpu_vm_flush(ring, job->vmid, job->vm_pd_addr);
+               amdgpu_ring_emit_vm_flush(ring, job->vmid, job->vm_pd_addr);
 
                r = amdgpu_fence_emit(ring, &fence);
                if (r)
@@ -532,7 +532,7 @@ int amdgpu_vm_flush(struct amdgpu_ring *ring, struct amdgpu_job *job, bool need_
                id->gws_size = job->gws_size;
                id->oa_base = job->oa_base;
                id->oa_size = job->oa_size;
-               amdgpu_ring_emit_gds_switch(ring, job->vm_id, job->gds_base,
+               amdgpu_ring_emit_gds_switch(ring, job->vmid, job->gds_base,
                                            job->gds_size, job->gws_base,
                                            job->gws_size, job->oa_base,
                                            job->oa_size);

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_ih.c b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
index a870b354e3f7babc8e24f36929f9792d1cb65f36..d5a05c19708fc9f4fdde684d7d7a19d282ffa45c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_ih.c
@@ -280,7 +280,7 @@ static void cik_ih_decode_iv(struct amdgpu_device *adev,
        entry->src_id = dw[0] & 0xff;
        entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
-       entry->vm_id = (dw[2] >> 8) & 0xff;
+       entry->vmid = (dw[2] >> 8) & 0xff;
        entry->pas_id = (dw[2] >> 16) & 0xffff;
 
        /* wptr/rptr are in bytes! */

diff --git a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
index e406c93d01d65a56a213c9bb51d1a031da766cd3..6e8278e689b18ef35bd67428573cc8dd15c5dcbe 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
+++ b/drivers/gpu/drm/amd/amdgpu/cik_sdma.c
@@ -221,9 +221,9 @@ static void cik_sdma_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  */
 static void cik_sdma_ring_emit_ib(struct amdgpu_ring *ring,
                                  struct amdgpu_ib *ib,
-                                 unsigned vm_id, bool ctx_switch)
+                                 unsigned vmid, bool ctx_switch)
 {
-       u32 extra_bits = vm_id & 0xf;
+       u32 extra_bits = vmid & 0xf;
 
        /* IB packet must end on a 8 DW boundary */
        cik_sdma_ring_insert_nop(ring, (12 - (lower_32_bits(ring->wptr) & 7)) % 8);
@@ -880,23 +880,23 @@ static void cik_sdma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
  * using sDMA (CIK).
  */
 static void cik_sdma_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                       unsigned vm_id, uint64_t pd_addr)
+                                       unsigned vmid, uint64_t pd_addr)
 {
        u32 extra_bits = (SDMA_POLL_REG_MEM_EXTRA_OP(0) |
                          SDMA_POLL_REG_MEM_EXTRA_FUNC(0)); /* always */
 
        amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
-       if (vm_id < 8) {
-               amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+       if (vmid < 8) {
+               amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
        } else {
-               amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+               amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
        }
        amdgpu_ring_write(ring, pd_addr >> 12);
 
        /* flush TLB */
        amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_SRBM_WRITE, 0, 0xf000));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
 
        amdgpu_ring_write(ring, SDMA_PACKET(SDMA_OPCODE_POLL_REG_MEM, 0, extra_bits));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);

diff --git a/drivers/gpu/drm/amd/amdgpu/cz_ih.c b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
index fa61d649bb44a5c89126bd7cd680ad88c39ce52f..f576e9cbbc61c613551770fee2f4159dba9f4f8a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/cz_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/cz_ih.c
@@ -259,7 +259,7 @@ static void cz_ih_decode_iv(struct amdgpu_device *adev,
        entry->src_id = dw[0] & 0xff;
        entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
-       entry->vm_id = (dw[2] >> 8) & 0xff;
+       entry->vmid = (dw[2] >> 8) & 0xff;
        entry->pas_id = (dw[2] >> 16) & 0xffff;
 
        /* wptr/rptr are in bytes! */

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
index edef17d93527a585a8379ce4bc4c29f5a14b14b2..9870d83b68c17448df2df0ba770801d4c2329132 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v6_0.c
@@ -1874,7 +1874,7 @@ static void gfx_v6_0_ring_emit_fence(struct amdgpu_ring *ring, u64 addr,
 
 static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
                                  struct amdgpu_ib *ib,
-                                 unsigned vm_id, bool ctx_switch)
+                                 unsigned vmid, bool ctx_switch)
 {
        u32 header, control = 0;
 
@@ -1889,7 +1889,7 @@ static void gfx_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
        else
                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-       control |= ib->length_dw | (vm_id << 24);
+       control |= ib->length_dw | (vmid << 24);
 
        amdgpu_ring_write(ring, header);
        amdgpu_ring_write(ring,
@@ -2354,7 +2354,7 @@ static void gfx_v6_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 }
 
 static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                       unsigned vm_id, uint64_t pd_addr)
+                                       unsigned vmid, uint64_t pd_addr)
 {
        int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
@@ -2362,10 +2362,10 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(1) |
                                 WRITE_DATA_DST_SEL(0)));
-       if (vm_id < 8) {
-               amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id ));
+       if (vmid < 8) {
+               amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid ));
        } else {
-               amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
+               amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
        }
        amdgpu_ring_write(ring, 0);
        amdgpu_ring_write(ring, pd_addr >> 12);
@@ -2376,7 +2376,7 @@ static void gfx_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                 WRITE_DATA_DST_SEL(0)));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
        amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
 
        /* wait for the invalidate to complete */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
index 83d94c23aa782846367a90a828d7137d7a464aeb..4b5109bfd5f4bdf01a812d8da4e4491317f5d894 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v7_0.c
@@ -2252,7 +2252,7 @@ static void gfx_v7_0_ring_emit_fence_compute(struct amdgpu_ring *ring,
  */
 static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                      struct amdgpu_ib *ib,
-                                     unsigned vm_id, bool ctx_switch)
+                                     unsigned vmid, bool ctx_switch)
 {
        u32 header, control = 0;
 
@@ -2267,7 +2267,7 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
        else
                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-       control |= ib->length_dw | (vm_id << 24);
+       control |= ib->length_dw | (vmid << 24);
 
        amdgpu_ring_write(ring, header);
        amdgpu_ring_write(ring,
@@ -2281,9 +2281,9 @@ static void gfx_v7_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 static void gfx_v7_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
                                          struct amdgpu_ib *ib,
-                                         unsigned vm_id, bool ctx_switch)
+                                         unsigned vmid, bool ctx_switch)
 {
-       u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
+       u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
        amdgpu_ring_write(ring,
@@ -3237,19 +3237,19 @@ static void gfx_v7_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
  * using the CP (CIK).
  */
 static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                       unsigned vm_id, uint64_t pd_addr)
+                                       unsigned vmid, uint64_t pd_addr)
 {
        int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_WRITE_DATA, 3));
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
                                 WRITE_DATA_DST_SEL(0)));
-       if (vm_id < 8) {
+       if (vmid < 8) {
                amdgpu_ring_write(ring,
-                                 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+                                 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
        } else {
                amdgpu_ring_write(ring,
-                                 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+                                 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
        }
        amdgpu_ring_write(ring, 0);
        amdgpu_ring_write(ring, pd_addr >> 12);
@@ -3260,7 +3260,7 @@ static void gfx_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                 WRITE_DATA_DST_SEL(0)));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
        amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
 
        /* wait for the invalidate to complete */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
index 46550b5889825fef90c56a69f00ce01c49dc5df6..ff9f1a82630f66f53013d3391daff4b95f7f08ff 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v8_0.c
@@ -6245,7 +6245,7 @@ static void gfx_v8_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 
 static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                      struct amdgpu_ib *ib,
-                                     unsigned vm_id, bool ctx_switch)
+                                     unsigned vmid, bool ctx_switch)
 {
        u32 header, control = 0;
 
@@ -6254,7 +6254,7 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
        else
                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-       control |= ib->length_dw | (vm_id << 24);
+       control |= ib->length_dw | (vmid << 24);
 
        if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
                control |= INDIRECT_BUFFER_PRE_ENB(1);
@@ -6275,9 +6275,9 @@ static void gfx_v8_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
 
 static void gfx_v8_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
                                          struct amdgpu_ib *ib,
-                                         unsigned vm_id, bool ctx_switch)
+                                         unsigned vmid, bool ctx_switch)
 {
-       u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
+       u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
 
        amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
        amdgpu_ring_write(ring,
@@ -6328,7 +6328,7 @@ static void gfx_v8_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 }
 
 static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                       unsigned vm_id, uint64_t pd_addr)
+                                       unsigned vmid, uint64_t pd_addr)
 {
        int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
 
@@ -6336,12 +6336,12 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, (WRITE_DATA_ENGINE_SEL(usepfp) |
                                 WRITE_DATA_DST_SEL(0)) |
                                 WR_CONFIRM);
-       if (vm_id < 8) {
+       if (vmid < 8) {
                amdgpu_ring_write(ring,
-                                 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+                                 (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
        } else {
                amdgpu_ring_write(ring,
-                                 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+                                 (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
        }
        amdgpu_ring_write(ring, 0);
        amdgpu_ring_write(ring, pd_addr >> 12);
@@ -6353,7 +6353,7 @@ static void gfx_v8_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                                 WRITE_DATA_DST_SEL(0)));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
        amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
 
        /* wait for the invalidate to complete */
        amdgpu_ring_write(ring, PACKET3(PACKET3_WAIT_REG_MEM, 5));

diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
index 9f7be230734c5a4d99b107dadba77e5530b82598..55670dbacaceaab7fd3b96eaab034fb9a32f583c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c
@@ -3594,7 +3594,7 @@ static void gfx_v9_0_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
 
 static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
                                       struct amdgpu_ib *ib,
-                                      unsigned vm_id, bool ctx_switch)
+                                      unsigned vmid, bool ctx_switch)
 {
        u32 header, control = 0;
 
@@ -3603,7 +3603,7 @@ static void gfx_v9_0_ring_emit_ib_gfx(struct amdgpu_ring *ring,
        else
                header = PACKET3(PACKET3_INDIRECT_BUFFER, 2);
 
-       control |= ib->length_dw | (vm_id << 24);
+       control |= ib->length_dw | (vmid << 24);
 
        if (amdgpu_sriov_vf(ring->adev) && (ib->flags & AMDGPU_IB_FLAG_PREEMPT)) {
                control |= INDIRECT_BUFFER_PRE_ENB(1);
@@ -3625,9 +3625,9 @@ BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
 
 static void gfx_v9_0_ring_emit_ib_compute(struct amdgpu_ring *ring,
                                           struct amdgpu_ib *ib,
-                                          unsigned vm_id, bool ctx_switch)
+                                          unsigned vmid, bool ctx_switch)
 {
-        u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vm_id << 24);
+        u32 control = INDIRECT_BUFFER_VALID | ib->length_dw | (vmid << 24);
 
         amdgpu_ring_write(ring, PACKET3(PACKET3_INDIRECT_BUFFER, 2));
        BUG_ON(ib->gpu_addr & 0x3); /* Dword align */
@@ -3683,11 +3683,11 @@ static void gfx_v9_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
 }
 
 static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                       unsigned vm_id, uint64_t pd_addr)
+                                       unsigned vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
        int usepfp = (ring->funcs->type == AMDGPU_RING_TYPE_GFX);
-       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
        uint64_t flags = AMDGPU_PTE_VALID;
        unsigned eng = ring->vm_inv_eng;
 
@@ -3695,11 +3695,11 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        pd_addr |= flags;
 
        gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-                                  hub->ctx0_ptb_addr_lo32 + (2 * vm_id),
+                                  hub->ctx0_ptb_addr_lo32 + (2 * vmid),
                                   lower_32_bits(pd_addr));
 
        gfx_v9_0_write_data_to_reg(ring, usepfp, true,
-                                  hub->ctx0_ptb_addr_hi32 + (2 * vm_id),
+                                  hub->ctx0_ptb_addr_hi32 + (2 * vmid),
                                   upper_32_bits(pd_addr));
 
        gfx_v9_0_write_data_to_reg(ring, usepfp, true,
@@ -3707,7 +3707,7 @@ static void gfx_v9_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
        /* wait for the invalidate to complete */
        gfx_v9_0_wait_reg_mem(ring, 0, 0, 0, hub->vm_inv_eng0_ack +
-                             eng, 0, 1 << vm_id, 1 << vm_id, 0x20);
+                             eng, 0, 1 << vmid, 1 << vmid, 0x20);
 
        /* compute doesn't have PFP */
        if (usepfp) {

diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
index 909274e3ebe704a3997f200f8bf822e2a63597b9..eb8b1bb66389522991599827c5ed407a000bbe91 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v9_0.c
@@ -248,7 +248,7 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
                                struct amdgpu_irq_src *source,
                                struct amdgpu_iv_entry *entry)
 {
-       struct amdgpu_vmhub *hub = &adev->vmhub[entry->vm_id_src];
+       struct amdgpu_vmhub *hub = &adev->vmhub[entry->vmid_src];
        uint32_t status = 0;
        u64 addr;
 
@@ -262,9 +262,9 @@ static int gmc_v9_0_process_interrupt(struct amdgpu_device *adev,
 
        if (printk_ratelimit()) {
                dev_err(adev->dev,
-                       "[%s] VMC page fault (src_id:%u ring:%u vm_id:%u pas_id:%u)\n",
-                       entry->vm_id_src ? "mmhub" : "gfxhub",
-                       entry->src_id, entry->ring_id, entry->vm_id,
+                       "[%s] VMC page fault (src_id:%u ring:%u vmid:%u pas_id:%u)\n",
+                       entry->vmid_src ? "mmhub" : "gfxhub",
+                       entry->src_id, entry->ring_id, entry->vmid,
                        entry->pas_id);
                dev_err(adev->dev, "  at page 0x%016llx from %d\n",
                        addr, entry->client_id);
@@ -288,13 +288,13 @@ static void gmc_v9_0_set_irq_funcs(struct amdgpu_device *adev)
        adev->mc.vm_fault.funcs = &gmc_v9_0_irq_funcs;
 }
 
-static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vm_id)
+static uint32_t gmc_v9_0_get_invalidate_req(unsigned int vmid)
 {
        u32 req = 0;
 
-       /* invalidate using legacy mode on vm_id*/
+       /* invalidate using legacy mode on vmid*/
        req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ,
-                           PER_VMID_INVALIDATE_REQ, 1 << vm_id);
+                           PER_VMID_INVALIDATE_REQ, 1 << vmid);
        req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, FLUSH_TYPE, 0);
        req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PTES, 1);
        req = REG_SET_FIELD(req, VM_INVALIDATE_ENG0_REQ, INVALIDATE_L2_PDE0, 1);

diff --git a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
index bd592cb39f3708d72c645aecda67ca09fd521272..c4e4be3dd31d87de5af944b50ec97e2e2bac628e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/iceland_ih.c
@@ -259,7 +259,7 @@ static void iceland_ih_decode_iv(struct amdgpu_device *adev,
        entry->src_id = dw[0] & 0xff;
        entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
-       entry->vm_id = (dw[2] >> 8) & 0xff;
+       entry->vmid = (dw[2] >> 8) & 0xff;
        entry->pas_id = (dw[2] >> 16) & 0xffff;
 
        /* wptr/rptr are in bytes! */

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
index 401552bae7f5be35dfe0dca5e464c09387883d42..d4787ad4d346b0592f8e90103410df3cf860c59e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v2_4.c
@@ -246,15 +246,13 @@ static void sdma_v2_4_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  */
 static void sdma_v2_4_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_ib *ib,
-                                  unsigned vm_id, bool ctx_switch)
+                                  unsigned vmid, bool ctx_switch)
 {
-       u32 vmid = vm_id & 0xf;
-
        /* IB packet must end on a 8 DW boundary */
        sdma_v2_4_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
-                         SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
+                         SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
        /* base must be 32 byte aligned */
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -861,14 +859,14 @@ static void sdma_v2_4_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
  * using sDMA (VI).
  */
 static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                        unsigned vm_id, uint64_t pd_addr)
+                                        unsigned vmid, uint64_t pd_addr)
 {
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       if (vm_id < 8) {
-               amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+       if (vmid < 8) {
+               amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
        } else {
-               amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+               amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
        }
        amdgpu_ring_write(ring, pd_addr >> 12);
 
@@ -876,7 +874,7 @@ static void sdma_v2_4_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
 
        /* wait for flush */
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
index 0735d4d0e56af6f18f85ef3dc8f848491bd117c9..521978c4053744abae0061ea04d41af362a9f443 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v3_0.c
@@ -417,15 +417,13 @@ static void sdma_v3_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  */
 static void sdma_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
                                   struct amdgpu_ib *ib,
-                                  unsigned vm_id, bool ctx_switch)
+                                  unsigned vmid, bool ctx_switch)
 {
-       u32 vmid = vm_id & 0xf;
-
        /* IB packet must end on a 8 DW boundary */
        sdma_v3_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
-                         SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
+                         SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
        /* base must be 32 byte aligned */
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -1127,14 +1125,14 @@ static void sdma_v3_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
  * using sDMA (VI).
  */
 static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                        unsigned vm_id, uint64_t pd_addr)
+                                        unsigned vmid, uint64_t pd_addr)
 {
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       if (vm_id < 8) {
-               amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+       if (vmid < 8) {
+               amdgpu_ring_write(ring, (mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
        } else {
-               amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8));
+               amdgpu_ring_write(ring, (mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8));
        }
        amdgpu_ring_write(ring, pd_addr >> 12);
 
@@ -1142,7 +1140,7 @@ static void sdma_v3_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
 
        /* wait for flush */
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_POLL_REGMEM) |

diff --git a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
index 73477c5ed9b4442c1ef2ea198df13221ecd99796..e92fb372bc99738dad957334ba40d3a138c57636 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/sdma_v4_0.c
@@ -330,15 +330,13 @@ static void sdma_v4_0_ring_insert_nop(struct amdgpu_ring *ring, uint32_t count)
  */
 static void sdma_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
                                        struct amdgpu_ib *ib,
-                                       unsigned vm_id, bool ctx_switch)
+                                       unsigned vmid, bool ctx_switch)
 {
-       u32 vmid = vm_id & 0xf;
-
        /* IB packet must end on a 8 DW boundary */
        sdma_v4_0_ring_insert_nop(ring, (10 - (lower_32_bits(ring->wptr) & 7)) % 8);
 
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_INDIRECT) |
-                         SDMA_PKT_INDIRECT_HEADER_VMID(vmid));
+                         SDMA_PKT_INDIRECT_HEADER_VMID(vmid & 0xf));
        /* base must be 32 byte aligned */
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0);
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
@@ -1135,10 +1133,10 @@ static void sdma_v4_0_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
  * using sDMA (VEGA10).
  */
 static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                        unsigned vm_id, uint64_t pd_addr)
+                                        unsigned vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
        uint64_t flags = AMDGPU_PTE_VALID;
        unsigned eng = ring->vm_inv_eng;
 
@@ -1147,12 +1145,12 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vm_id * 2);
+       amdgpu_ring_write(ring, hub->ctx0_ptb_addr_lo32 + vmid * 2);
        amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
        amdgpu_ring_write(ring, SDMA_PKT_HEADER_OP(SDMA_OP_SRBM_WRITE) |
                          SDMA_PKT_SRBM_WRITE_HEADER_BYTE_EN(0xf));
-       amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vm_id * 2);
+       amdgpu_ring_write(ring, hub->ctx0_ptb_addr_hi32 + vmid * 2);
        amdgpu_ring_write(ring, upper_32_bits(pd_addr));
 
        /* flush TLB */
@@ -1167,8 +1165,8 @@ static void sdma_v4_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
                          SDMA_PKT_POLL_REGMEM_HEADER_FUNC(3)); /* equal */
        amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
        amdgpu_ring_write(ring, 0);
-       amdgpu_ring_write(ring, 1 << vm_id); /* reference */
-       amdgpu_ring_write(ring, 1 << vm_id); /* mask */
+       amdgpu_ring_write(ring, 1 << vmid); /* reference */
+       amdgpu_ring_write(ring, 1 << vmid); /* mask */
        amdgpu_ring_write(ring, SDMA_PKT_POLL_REGMEM_DW5_RETRY_COUNT(0xfff) |
                          SDMA_PKT_POLL_REGMEM_DW5_INTERVAL(10));
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/si_dma.c b/drivers/gpu/drm/amd/amdgpu/si_dma.c
index 9adca5d8b04589c989cf64a343a8d2e48ba2ae64..9a29c13990918116a2bbfdaca9a9043f757dbc3c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si_dma.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_dma.c
@@ -61,14 +61,14 @@ static void si_dma_ring_set_wptr(struct amdgpu_ring *ring)
 
 static void si_dma_ring_emit_ib(struct amdgpu_ring *ring,
                                struct amdgpu_ib *ib,
-                               unsigned vm_id, bool ctx_switch)
+                               unsigned vmid, bool ctx_switch)
 {
        /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring.
         * Pad as necessary with NOPs.
         */
        while ((lower_32_bits(ring->wptr) & 7) != 5)
                amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0, 0));
-       amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0));
+       amdgpu_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vmid, 0));
        amdgpu_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0));
        amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF));
 
@@ -473,25 +473,25 @@ static void si_dma_ring_emit_pipeline_sync(struct amdgpu_ring *ring)
  * using sDMA (VI).
  */
 static void si_dma_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                     unsigned vm_id, uint64_t pd_addr)
+                                     unsigned vmid, uint64_t pd_addr)
 {
        amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
-       if (vm_id < 8)
-               amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id));
+       if (vmid < 8)
+               amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid));
        else
-               amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vm_id - 8)));
+               amdgpu_ring_write(ring, (0xf << 16) | (VM_CONTEXT8_PAGE_TABLE_BASE_ADDR + (vmid - 8)));
        amdgpu_ring_write(ring, pd_addr >> 12);
 
        /* bits 0-7 are the VM contexts0-7 */
        amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0, 0));
        amdgpu_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST));
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
 
        /* wait for invalidate to complete */
        amdgpu_ring_write(ring, DMA_PACKET(DMA_PACKET_POLL_REG_MEM, 0, 0, 0, 0));
        amdgpu_ring_write(ring, VM_INVALIDATE_REQUEST);
        amdgpu_ring_write(ring, 0xff << 16); /* retry */
-       amdgpu_ring_write(ring, 1 << vm_id); /* mask */
+       amdgpu_ring_write(ring, 1 << vmid); /* mask */
        amdgpu_ring_write(ring, 0); /* value */
        amdgpu_ring_write(ring, (0 << 28) | 0x20); /* func(always) | poll interval */
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/si_ih.c b/drivers/gpu/drm/amd/amdgpu/si_ih.c
index d2c6b80309c8db3560968bc80577a0628ee675b0..60dad63098a2aa4db47de4804174a992fb78039e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/si_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/si_ih.c
@@ -146,7 +146,7 @@ static void si_ih_decode_iv(struct amdgpu_device *adev,
        entry->src_id = dw[0] & 0xff;
        entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
-       entry->vm_id = (dw[2] >> 8) & 0xff;
+       entry->vmid = (dw[2] >> 8) & 0xff;
 
        adev->irq.ih.rptr += 16;
 }

diff --git a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
index aa4e320e31f8b82178aaa7d2ed21c74b03209149..5995ffc183de0612c1f64fd6aa76e6874b71efdd 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/tonga_ih.c
@@ -270,7 +270,7 @@ static void tonga_ih_decode_iv(struct amdgpu_device *adev,
        entry->src_id = dw[0] & 0xff;
        entry->src_data[0] = dw[1] & 0xfffffff;
        entry->ring_id = dw[2] & 0xff;
-       entry->vm_id = (dw[2] >> 8) & 0xff;
+       entry->vmid = (dw[2] >> 8) & 0xff;
        entry->pas_id = (dw[2] >> 16) & 0xffff;
 
        /* wptr/rptr are in bytes! */

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
index b13ae34be1c2f6d0466ffe905be74472a1faaed5..8ab10c220910c6a176ff7fe36e1c945eda3ecfe0 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v4_2.c
@@ -541,7 +541,7 @@ static int uvd_v4_2_ring_test_ring(struct amdgpu_ring *ring)
  */
 static void uvd_v4_2_ring_emit_ib(struct amdgpu_ring *ring,
                                  struct amdgpu_ib *ib,
-                                 unsigned vm_id, bool ctx_switch)
+                                 unsigned vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, PACKET0(mmUVD_RBC_IB_BASE, 0));
        amdgpu_ring_write(ring, ib->gpu_addr);

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
index a4b0f1d842b734aedd2c74f3361bdbbd24879889..c1fe30cdba32021532123fa2174ac89ee745436e 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v5_0.c
@@ -556,7 +556,7 @@ static int uvd_v5_0_ring_test_ring(struct amdgpu_ring *ring)
  */
 static void uvd_v5_0_ring_emit_ib(struct amdgpu_ring *ring,
                                  struct amdgpu_ib *ib,
-                                 unsigned vm_id, bool ctx_switch)
+                                 unsigned vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
index 86123448a8fffbc03d985566cc217a11db6443d8..59271055a30e71f0ecdc34e9ca188efdbfa4341c 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v6_0.c
@@ -1028,10 +1028,10 @@ static int uvd_v6_0_ring_test_ring(struct amdgpu_ring *ring)
  */
 static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
                                  struct amdgpu_ib *ib,
-                                 unsigned vm_id, bool ctx_switch)
+                                 unsigned vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_VMID, 0));
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
 
        amdgpu_ring_write(ring, PACKET0(mmUVD_LMI_RBC_IB_64BIT_BAR_LOW, 0));
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
@@ -1050,24 +1050,24 @@ static void uvd_v6_0_ring_emit_ib(struct amdgpu_ring *ring,
  * Write enc ring commands to execute the indirect buffer
  */
 static void uvd_v6_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
-               struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+               struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, ib->length_dw);
 }
 
 static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                        unsigned vm_id, uint64_t pd_addr)
+                                        unsigned vmid, uint64_t pd_addr)
 {
        uint32_t reg;
 
-       if (vm_id < 8)
-               reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vm_id;
+       if (vmid < 8)
+               reg = mmVM_CONTEXT0_PAGE_TABLE_BASE_ADDR + vmid;
        else
-               reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vm_id - 8;
+               reg = mmVM_CONTEXT8_PAGE_TABLE_BASE_ADDR + vmid - 8;
 
        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
        amdgpu_ring_write(ring, reg << 2);
@@ -1079,7 +1079,7 @@ static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0));
        amdgpu_ring_write(ring, mmVM_INVALIDATE_REQUEST << 2);
        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
        amdgpu_ring_write(ring, 0x8);
 
@@ -1088,7 +1088,7 @@ static void uvd_v6_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0));
        amdgpu_ring_write(ring, 0);
        amdgpu_ring_write(ring, PACKET0(mmUVD_GP_SCRATCH8, 0));
-       amdgpu_ring_write(ring, 1 << vm_id); /* mask */
+       amdgpu_ring_write(ring, 1 << vmid); /* mask */
        amdgpu_ring_write(ring, PACKET0(mmUVD_GPCOM_VCPU_CMD, 0));
        amdgpu_ring_write(ring, 0xC);
 }
@@ -1127,14 +1127,14 @@ static void uvd_v6_0_enc_ring_insert_end(struct amdgpu_ring *ring)
 }
 
 static void uvd_v6_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
-        unsigned int vm_id, uint64_t pd_addr)
+        unsigned int vmid, uint64_t pd_addr)
 {
        amdgpu_ring_write(ring, HEVC_ENC_CMD_UPDATE_PTB);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
        amdgpu_ring_write(ring, pd_addr >> 12);
 
        amdgpu_ring_write(ring, HEVC_ENC_CMD_FLUSH_TLB);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
 }
 
 static bool uvd_v6_0_is_idle(void *handle)

diff --git a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
index 4ec4447d33c040f82569de0dca45511aa7345aa8..6b95f4f344b5315cb295a28a0868f008b8652acb 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/uvd_v7_0.c
@@ -1218,13 +1218,13 @@ static int uvd_v7_0_ring_test_ring(struct amdgpu_ring *ring)
  */
 static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
                                  struct amdgpu_ib *ib,
-                                 unsigned vm_id, bool ctx_switch)
+                                 unsigned vmid, bool ctx_switch)
 {
        struct amdgpu_device *adev = ring->adev;
 
        amdgpu_ring_write(ring,
                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
 
        amdgpu_ring_write(ring,
                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
@@ -1246,10 +1246,10 @@ static void uvd_v7_0_ring_emit_ib(struct amdgpu_ring *ring,
  * Write enc ring commands to execute the indirect buffer
  */
 static void uvd_v7_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
-               struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+               struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, HEVC_ENC_CMD_IB_VM);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, ib->length_dw);
@@ -1291,10 +1291,10 @@ static void uvd_v7_0_vm_reg_wait(struct amdgpu_ring *ring,
 }
 
 static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                       unsigned vm_id, uint64_t pd_addr)
+                                       unsigned vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
        uint64_t flags = AMDGPU_PTE_VALID;
        unsigned eng = ring->vm_inv_eng;
        uint32_t data0, data1, mask;
@@ -1302,15 +1302,15 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
        pd_addr |= flags;
 
-       data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
+       data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
        data1 = upper_32_bits(pd_addr);
        uvd_v7_0_vm_reg_write(ring, data0, data1);
 
-       data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+       data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
        data1 = lower_32_bits(pd_addr);
        uvd_v7_0_vm_reg_write(ring, data0, data1);
 
-       data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+       data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
        data1 = lower_32_bits(pd_addr);
        mask = 0xffffffff;
        uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
@@ -1322,8 +1322,8 @@ static void uvd_v7_0_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
        /* wait for flush */
        data0 = (hub->vm_inv_eng0_ack + eng) << 2;
-       data1 = 1 << vm_id;
-       mask =  1 << vm_id;
+       data1 = 1 << vmid;
+       mask =  1 << vmid;
        uvd_v7_0_vm_reg_wait(ring, data0, data1, mask);
 }
 
@@ -1343,10 +1343,10 @@ static void uvd_v7_0_enc_ring_insert_end(struct amdgpu_ring *ring)
 }
 
 static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                        unsigned int vm_id, uint64_t pd_addr)
+                        unsigned int vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
        uint64_t flags = AMDGPU_PTE_VALID;
        unsigned eng = ring->vm_inv_eng;
 
@@ -1354,15 +1354,15 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
        pd_addr |= flags;
 
        amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
-       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, upper_32_bits(pd_addr));
 
        amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WRITE);
-       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
        amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
-       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, 0xffffffff);
        amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
@@ -1374,8 +1374,8 @@ static void uvd_v7_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
        /* wait for flush */
        amdgpu_ring_write(ring, HEVC_ENC_CMD_REG_WAIT);
        amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
-       amdgpu_ring_write(ring, 1 << vm_id);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
+       amdgpu_ring_write(ring, 1 << vmid);
 }
 
 #if 0

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
index cf81065e3c5ab95030f24f4a883924f27c71bc90..a5355eb689f145a81ec8296d8cfdcc27600b0012 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v3_0.c
@@ -834,24 +834,24 @@ out:
 }
 
 static void vce_v3_0_ring_emit_ib(struct amdgpu_ring *ring,
-               struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+               struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, VCE_CMD_IB_VM);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, ib->length_dw);
 }
 
 static void vce_v3_0_emit_vm_flush(struct amdgpu_ring *ring,
-                        unsigned int vm_id, uint64_t pd_addr)
+                        unsigned int vmid, uint64_t pd_addr)
 {
        amdgpu_ring_write(ring, VCE_CMD_UPDATE_PTB);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
        amdgpu_ring_write(ring, pd_addr >> 12);
 
        amdgpu_ring_write(ring, VCE_CMD_FLUSH_TLB);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
        amdgpu_ring_write(ring, VCE_CMD_END);
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
index 308949d6eddef6c55cc8a31aff09016c2372c8b0..7cf2eef68cf24d32c1dc2b50dacd78ccc58d9b3b 100755 (executable)
--- a/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vce_v4_0.c
@@ -938,10 +938,10 @@ static int vce_v4_0_set_powergating_state(void *handle,
 #endif
 
 static void vce_v4_0_ring_emit_ib(struct amdgpu_ring *ring,
-               struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+               struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, VCE_CMD_IB_VM);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, ib->length_dw);
@@ -965,10 +965,10 @@ static void vce_v4_0_ring_insert_end(struct amdgpu_ring *ring)
 }
 
 static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
-                        unsigned int vm_id, uint64_t pd_addr)
+                        unsigned int vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
        uint64_t flags = AMDGPU_PTE_VALID;
        unsigned eng = ring->vm_inv_eng;
 
@@ -976,15 +976,15 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
        pd_addr |= flags;
 
        amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
-       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, upper_32_bits(pd_addr));
 
        amdgpu_ring_write(ring, VCE_CMD_REG_WRITE);
-       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
        amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
-       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+       amdgpu_ring_write(ring, (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, 0xffffffff);
        amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
@@ -996,8 +996,8 @@ static void vce_v4_0_emit_vm_flush(struct amdgpu_ring *ring,
        /* wait for flush */
        amdgpu_ring_write(ring, VCE_CMD_REG_WAIT);
        amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
-       amdgpu_ring_write(ring, 1 << vm_id);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
+       amdgpu_ring_write(ring, 1 << vmid);
 }
 
 static int vce_v4_0_set_interrupt_state(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
index deb3fba790a54a48bebc54ed4e8215d23b3d8dd7..b99e15c43e45cf847b4699f86e5e1c24187fe279 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v1_0.c
@@ -833,13 +833,13 @@ static void vcn_v1_0_dec_ring_emit_hdp_invalidate(struct amdgpu_ring *ring)
  */
 static void vcn_v1_0_dec_ring_emit_ib(struct amdgpu_ring *ring,
                                  struct amdgpu_ib *ib,
-                                 unsigned vm_id, bool ctx_switch)
+                                 unsigned vmid, bool ctx_switch)
 {
        struct amdgpu_device *adev = ring->adev;
 
        amdgpu_ring_write(ring,
                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_VMID), 0));
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
 
        amdgpu_ring_write(ring,
                PACKET0(SOC15_REG_OFFSET(UVD, 0, mmUVD_LMI_RBC_IB_64BIT_BAR_LOW), 0));
@@ -888,10 +888,10 @@ static void vcn_v1_0_dec_vm_reg_wait(struct amdgpu_ring *ring,
 }
 
 static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                                       unsigned vm_id, uint64_t pd_addr)
+                                       unsigned vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
        uint64_t flags = AMDGPU_PTE_VALID;
        unsigned eng = ring->vm_inv_eng;
        uint32_t data0, data1, mask;
@@ -899,15 +899,15 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
        amdgpu_gart_get_vm_pde(ring->adev, -1, &pd_addr, &flags);
        pd_addr |= flags;
 
-       data0 = (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2;
+       data0 = (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2;
        data1 = upper_32_bits(pd_addr);
        vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
 
-       data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+       data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
        data1 = lower_32_bits(pd_addr);
        vcn_v1_0_dec_vm_reg_write(ring, data0, data1);
 
-       data0 = (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2;
+       data0 = (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2;
        data1 = lower_32_bits(pd_addr);
        mask = 0xffffffff;
        vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
@@ -919,8 +919,8 @@ static void vcn_v1_0_dec_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
        /* wait for flush */
        data0 = (hub->vm_inv_eng0_ack + eng) << 2;
-       data1 = 1 << vm_id;
-       mask =  1 << vm_id;
+       data1 = 1 << vmid;
+       mask =  1 << vmid;
        vcn_v1_0_dec_vm_reg_wait(ring, data0, data1, mask);
 }
 
@@ -1011,20 +1011,20 @@ static void vcn_v1_0_enc_ring_insert_end(struct amdgpu_ring *ring)
  * Write enc ring commands to execute the indirect buffer
  */
 static void vcn_v1_0_enc_ring_emit_ib(struct amdgpu_ring *ring,
-               struct amdgpu_ib *ib, unsigned int vm_id, bool ctx_switch)
+               struct amdgpu_ib *ib, unsigned int vmid, bool ctx_switch)
 {
        amdgpu_ring_write(ring, VCN_ENC_CMD_IB);
-       amdgpu_ring_write(ring, vm_id);
+       amdgpu_ring_write(ring, vmid);
        amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr));
        amdgpu_ring_write(ring, ib->length_dw);
 }
 
 static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
-                        unsigned int vm_id, uint64_t pd_addr)
+                        unsigned int vmid, uint64_t pd_addr)
 {
        struct amdgpu_vmhub *hub = &ring->adev->vmhub[ring->funcs->vmhub];
-       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vm_id);
+       uint32_t req = ring->adev->gart.gart_funcs->get_invalidate_req(vmid);
        uint64_t flags = AMDGPU_PTE_VALID;
        unsigned eng = ring->vm_inv_eng;
 
@@ -1033,17 +1033,17 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
 
        amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
        amdgpu_ring_write(ring,
-                         (hub->ctx0_ptb_addr_hi32 + vm_id * 2) << 2);
+                         (hub->ctx0_ptb_addr_hi32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, upper_32_bits(pd_addr));
 
        amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WRITE);
        amdgpu_ring_write(ring,
-                         (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+                         (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
        amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
        amdgpu_ring_write(ring,
-                         (hub->ctx0_ptb_addr_lo32 + vm_id * 2) << 2);
+                         (hub->ctx0_ptb_addr_lo32 + vmid * 2) << 2);
        amdgpu_ring_write(ring, 0xffffffff);
        amdgpu_ring_write(ring, lower_32_bits(pd_addr));
 
@@ -1055,8 +1055,8 @@ static void vcn_v1_0_enc_ring_emit_vm_flush(struct amdgpu_ring *ring,
        /* wait for flush */
        amdgpu_ring_write(ring, VCN_ENC_CMD_REG_WAIT);
        amdgpu_ring_write(ring, (hub->vm_inv_eng0_ack + eng) << 2);
-       amdgpu_ring_write(ring, 1 << vm_id);
-       amdgpu_ring_write(ring, 1 << vm_id);
+       amdgpu_ring_write(ring, 1 << vmid);
+       amdgpu_ring_write(ring, 1 << vmid);
 }
 
 static int vcn_v1_0_set_interrupt_state(struct amdgpu_device *adev,

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index e1d7dae0989b20497b071a88a1453db0a4ee3238..b69ceafb78883e648609dab5927ed7049c720690 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -327,8 +327,8 @@ static void vega10_ih_decode_iv(struct amdgpu_device *adev,
        entry->client_id = dw[0] & 0xff;
        entry->src_id = (dw[0] >> 8) & 0xff;
        entry->ring_id = (dw[0] >> 16) & 0xff;
-       entry->vm_id = (dw[0] >> 24) & 0xf;
-       entry->vm_id_src = (dw[0] >> 31);
+       entry->vmid = (dw[0] >> 24) & 0xf;
+       entry->vmid_src = (dw[0] >> 31);
        entry->timestamp = dw[1] | ((u64)(dw[2] & 0xffff) << 32);
        entry->timestamp_src = dw[2] >> 31;
        entry->pas_id = dw[3] & 0xffff;