arm64: dts: exynos: Add MFC power domain to Exynos 5433 SoC

This patch adds support for MFC power domain to Exynos 5433 SoCs, which
contains following devices: a clock controller, MFC codec device and its
SYSMMUs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 0a06be283a31c2e32e41358d627528db42373426..cfa2a0d4dc2f8be904dcfbccfb62c9c903da2927 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -486,6 +486,7 @@
 
                        clock-names = "oscclk", "aclk_mfc_400";
                        clocks = <&xxti>, <&cmu_top CLK_ACLK_MFC_400>;
+                       power-domains = <&pd_mfc>;
                };
 
                cmu_hevc: clock-controller@14f80000 {
@@ -567,6 +568,13 @@
                        label = "DISP";
                };
 
+               pd_mfc: power-domain@105c4180 {
+                       compatible = "samsung,exynos5433-pd";
+                       reg = <0x105c4180 0x20>;
+                       #power-domain-cells = <0>;
+                       label = "MFC";
+               };
+
                tmu_atlas0: tmu@10060000 {
                        compatible = "samsung,exynos5433-tmu";
                        reg = <0x10060000 0x200>;
@@ -992,6 +1000,7 @@
                                 <&cmu_mfc CLK_ACLK_XIU_MFCX>;
                        iommus = <&sysmmu_mfc_0>, <&sysmmu_mfc_1>;
                        iommu-names = "left", "right";
+                       power-domains = <&pd_mfc>;
                };
 
                sysmmu_decon0x: sysmmu@13a00000 {
@@ -1090,6 +1099,7 @@
                        clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_0>,
                                 <&cmu_mfc CLK_ACLK_SMMU_MFC_0>;
                        #iommu-cells = <0>;
+                       power-domains = <&pd_mfc>;
                };
 
                sysmmu_mfc_1: sysmmu@15210000 {
@@ -1100,6 +1110,7 @@
                        clocks = <&cmu_mfc CLK_PCLK_SMMU_MFC_1>,
                                 <&cmu_mfc CLK_ACLK_SMMU_MFC_1>;
                        #iommu-cells = <0>;
+                       power-domains = <&pd_mfc>;
                };
 
                serial_0: serial@14c10000 {