u32 val;
        u8 stream_type;
 
-       val = intel_de_read(display, HDCP2_AUTH_STREAM(display, cpu_transcoder, port));
-       stream_type = REG_FIELD_GET(AUTH_STREAM_TYPE_MASK, val);
-       drm_WARN_ON(display->drm, enable &&
-                   stream_type != data->streams[0].stream_type);
+       if (DISPLAY_VER(display) < 30) {
+               val = intel_de_read(display,
+                                   HDCP2_AUTH_STREAM(display, cpu_transcoder, port));
+               stream_type = REG_FIELD_GET(AUTH_STREAM_TYPE_MASK, val);
+               drm_WARN_ON(display->drm, enable &&
+                           stream_type != data->streams[0].stream_type);
+       }
 
        ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
        if (ret)
                return -ETIMEDOUT;
        }
 
+       if (DISPLAY_VER(display) >= 30) {
+               val = intel_de_read(display,
+                                   HDCP2_STREAM_STATUS(display, cpu_transcoder, port));
+               stream_type = REG_FIELD_GET(STREAM_TYPE_STATUS_MASK, val);
+               drm_WARN_ON(display->drm, enable &&
+                           stream_type != data->streams[0].stream_type);
+       }
+
        return 0;
 }
 
 
                                                    _TRANSA_HDCP2_STREAM_STATUS, \
                                                    _TRANSB_HDCP2_STREAM_STATUS)
 #define   STREAM_ENCRYPTION_STATUS     REG_BIT(31)
-#define   STREAM_TYPE_STATUS           REG_BIT(30)
+#define   STREAM_TYPE_STATUS_MASK      REG_GENMASK(30, 30)
 #define HDCP2_STREAM_STATUS(dev_priv, trans, port) \
                                        (TRANS_HDCP(dev_priv) ? \
                                         TRANS_HDCP2_STREAM_STATUS(trans) : \