* - __u8
       - ``colour_plane_id``
       -
-    * - __u16
+    * - __s32
       - ``slice_pic_order_cnt``
       -
     * - __u8
 
                         !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));
 
        /*
-        * Write POC count diff from current pic. For frame decoding only compute
-        * pic_order_cnt[0] and ignore pic_order_cnt[1] used in field-coding.
+        * Write POC count diff from current pic.
         */
        for (i = 0; i < decode_params->num_active_dpb_entries && i < ARRAY_SIZE(cur_poc); i++) {
-               char poc_diff = decode_params->pic_order_cnt_val - dpb[i].pic_order_cnt[0];
+               char poc_diff = decode_params->pic_order_cnt_val - dpb[i].pic_order_cnt_val;
 
                hantro_reg_write(vpu, &cur_poc[i], poc_diff);
        }
        dpb_longterm_e = 0;
        for (i = 0; i < decode_params->num_active_dpb_entries &&
             i < (V4L2_HEVC_DPB_ENTRIES_NUM_MAX - 1); i++) {
-               luma_addr = hantro_hevc_get_ref_buf(ctx, dpb[i].pic_order_cnt[0]);
+               luma_addr = hantro_hevc_get_ref_buf(ctx, dpb[i].pic_order_cnt_val);
                if (!luma_addr)
                        return -ENOMEM;
 
 
 }
 
 dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx,
-                                  int poc)
+                                  s32 poc)
 {
        struct hantro_hevc_dec_hw_ctx *hevc_dec = &ctx->hevc_dec;
        int i;
 
        struct hantro_aux_buf tile_bsd;
        struct hantro_aux_buf ref_bufs[NUM_REF_PICTURES];
        struct hantro_aux_buf scaling_lists;
-       int ref_bufs_poc[NUM_REF_PICTURES];
+       s32 ref_bufs_poc[NUM_REF_PICTURES];
        u32 ref_bufs_used;
        struct hantro_hevc_dec_ctrls ctrls;
        unsigned int num_tile_cols_allocated;
 int hantro_g2_hevc_dec_run(struct hantro_ctx *ctx);
 int hantro_hevc_dec_prepare_run(struct hantro_ctx *ctx);
 void hantro_hevc_ref_init(struct hantro_ctx *ctx);
-dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, int poc);
+dma_addr_t hantro_hevc_get_ref_buf(struct hantro_ctx *ctx, s32 poc);
 int hantro_hevc_add_ref_buf(struct hantro_ctx *ctx, int poc, dma_addr_t addr);
 int hantro_hevc_validate_sps(struct hantro_ctx *ctx, const struct v4l2_ctrl_hevc_sps *sps);
 
 
        for (i = 0; i < num_active_dpb_entries; i++) {
                int buffer_index = vb2_find_timestamp(vq, dpb[i].timestamp, 0);
                u32 pic_order_cnt[2] = {
-                       dpb[i].pic_order_cnt[0],
-                       dpb[i].pic_order_cnt[1]
+                       dpb[i].pic_order_cnt_val,
+                       dpb[i].pic_order_cnt_val
                };
 
                cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic,
 
        __u64   timestamp;
        __u8    flags;
        __u8    field_pic;
-       __u16   pic_order_cnt[2];
+       __s32   pic_order_cnt_val;
        __u8    padding[2];
 };
 
        /* ISO/IEC 23008-2, ITU-T Rec. H.265: General slice segment header */
        __u8    slice_type;
        __u8    colour_plane_id;
-       __u16   slice_pic_order_cnt;
+       __s32   slice_pic_order_cnt;
        __u8    num_ref_idx_l0_active_minus1;
        __u8    num_ref_idx_l1_active_minus1;
        __u8    collocated_ref_idx;