x86: Add new MSRs and MSR bits used for Intel Skylake PMU support

Orabug: 23331091

[ Upstream commit b83ff1c8617aac03a1cf807aafa848fe0f0908f2 ]

Add new MSRs (LBR_INFO) and some new MSR bits used by the Intel Skylake
PMU driver.

Signed-off-by: Andi Kleen <ak@linux.intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: eranian@google.com
Link: http://lkml.kernel.org/r/1431285767-27027-4-git-send-email-andi@firstfloor.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
(cherry picked from commit c7af1256a07538167fe1b14a6714e7b92cf82179)

Signed-off-by: Dan Duval <dan.duval@oracle.com>

diff --git a/arch/x86/include/asm/perf_event.h b/arch/x86/include/asm/perf_event.h
index dc0f6ed35b0864d061f7383cab6055f9764995a6..7bcb861a04e5cf5b32c2c26919756fa29353cb07 100644 (file)
--- a/arch/x86/include/asm/perf_event.h
+++ b/arch/x86/include/asm/perf_event.h
@@ -159,6 +159,13 @@ struct x86_pmu_capability {
  */
 #define INTEL_PMC_IDX_FIXED_BTS                                (INTEL_PMC_IDX_FIXED + 16)
 
+#define GLOBAL_STATUS_COND_CHG                         BIT_ULL(63)
+#define GLOBAL_STATUS_BUFFER_OVF                       BIT_ULL(62)
+#define GLOBAL_STATUS_UNC_OVF                          BIT_ULL(61)
+#define GLOBAL_STATUS_ASIF                             BIT_ULL(60)
+#define GLOBAL_STATUS_COUNTERS_FROZEN                  BIT_ULL(59)
+#define GLOBAL_STATUS_LBRS_FROZEN                      BIT_ULL(58)
+
 /*
  * IBS cpuid feature detection
  */

diff --git a/arch/x86/include/uapi/asm/msr-index.h b/arch/x86/include/uapi/asm/msr-index.h
index 3c6bb342a48f1ad123ba82261c517c18266227b6..06b407f79b246b0564c2a65d2ddccf8f90bb9125 100644 (file)
--- a/arch/x86/include/uapi/asm/msr-index.h
+++ b/arch/x86/include/uapi/asm/msr-index.h
@@ -72,6 +72,12 @@
 #define MSR_LBR_CORE_FROM              0x00000040
 #define MSR_LBR_CORE_TO                        0x00000060
 
+#define MSR_LBR_INFO_0                 0x00000dc0 /* ... 0xddf for _31 */
+#define LBR_INFO_MISPRED               BIT_ULL(63)
+#define LBR_INFO_IN_TX                 BIT_ULL(62)
+#define LBR_INFO_ABORT                 BIT_ULL(61)
+#define LBR_INFO_CYCLES                        0xffff
+
 #define MSR_IA32_PEBS_ENABLE           0x000003f1
 #define MSR_IA32_DS_AREA               0x00000600
 #define MSR_IA32_PERF_CAPABILITIES     0x00000345