tcg_gen_andi_tl(test, dest, 3);
tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l);
- tcg_temp_free(test);
tcg_gen_mov_tl(cpu_pc, dest);
if (is_call) {
tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags);
- tcg_temp_free(addr);
}
/* Store instructions */
TCGv addr = tcg_temp_new();
tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s);
tcg_gen_qemu_st_tl(val, addr, dc->mem_idx, flags);
- tcg_temp_free(addr);
}
/* Branch instructions */
TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS]));
gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA));
- tcg_temp_free(tmp);
} else {
gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_EA));
}
TCGv tmp = tcg_temp_new();
tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS]));
gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA));
- tcg_temp_free(tmp);
dc->base.is_jmp = DISAS_NORETURN;
#endif
tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDING]));
tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE]));
tcg_gen_and_tl(dest, t1, t2);
- tcg_temp_free(t1);
- tcg_temp_free(t2);
break;
default:
tcg_gen_ld_tl(dest, cpu_env,
tcg_gen_ld_tl(o, cpu_env, ofs);
tcg_gen_andi_tl(o, o, ro);
tcg_gen_or_tl(n, n, o);
- tcg_temp_free(o);
}
tcg_gen_st_tl(n, cpu_env, ofs);
- tcg_temp_free(n);
}
break;
}
fn(discard, dest_gpr(dc, instr.c),
load_gpr(dc, instr.a), load_gpr(dc, instr.b));
- tcg_temp_free(discard);
}
#define gen_rr_mul_high(fname, insn) \
tcg_gen_andi_tl(sh, load_gpr(dc, instr.b), 31);
fn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), sh);
- tcg_temp_free(sh);
}
#define gen_rr_shift(fname, insn) \
instr = &i_type_instructions[op];
instr->handler(dc, code, instr->flags);
-
- if (dc->sink) {
- tcg_temp_free(dc->sink);
- }
}
static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs)