drm/i915/display/mtl: Program latch to phy reset

Latch reset of phys during DC9 and when driver is unloaded to avoid
phy reset.

Specification ask us to program it closer to the step that enables
DC9 in DC_STATE_EN but doing this way allow us to sanitize the phy
latch during driver load.

BSpec: 49197
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Signed-off-by: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20230301201053.928709-6-radhakrishna.sripada@intel.com

diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index f085ae9711508db1bf67ceae60bb275db0bd0536..f86060195987cb9dab91701bd9d1ef44569ea6ae 100644 (file)
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -1625,6 +1625,10 @@ static void icl_display_core_init(struct drm_i915_private *dev_priv,
        intel_power_well_enable(dev_priv, well);
        mutex_unlock(&power_domains->lock);
 
+       if (DISPLAY_VER(dev_priv) == 14)
+               intel_de_rmw(dev_priv, DC_STATE_EN,
+                            HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH, 0);
+
        /* 4. Enable CDCLK. */
        intel_cdclk_init_hw(dev_priv);
 
@@ -1678,6 +1682,10 @@ static void icl_display_core_uninit(struct drm_i915_private *dev_priv)
        /* 3. Disable CD clock */
        intel_cdclk_uninit_hw(dev_priv);
 
+       if (DISPLAY_VER(dev_priv) == 14)
+               intel_de_rmw(dev_priv, DC_STATE_EN, 0,
+                            HOLD_PHY_PG1_LATCH | HOLD_PHY_CLKREQ_PG1_LATCH);
+
        /*
         * 4. Disable Power Well 1 (PG1).
         *    The AUX IO power wells are toggled on demand, so they are already

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 9c30d292547d31aa7cfed82e565ad0a8a2fa5bc4..0ae084a8f7721f74e74c3a3e09fca201e08be697 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -7243,6 +7243,8 @@ enum skl_power_gate {
 #define  DC_STATE_DISABLE              0
 #define  DC_STATE_EN_DC3CO             REG_BIT(30)
 #define  DC_STATE_DC3CO_STATUS         REG_BIT(29)
+#define  HOLD_PHY_CLKREQ_PG1_LATCH     REG_BIT(21)
+#define  HOLD_PHY_PG1_LATCH            REG_BIT(20)
 #define  DC_STATE_EN_UPTO_DC5          (1 << 0)
 #define  DC_STATE_EN_DC9               (1 << 3)
 #define  DC_STATE_EN_UPTO_DC6          (2 << 0)