if (iosapic_intr_info[irq].count == 0) {
 #ifdef CONFIG_SMP
                /* Clear affinity */
-               cpumask_setall(irq_get_irq_data(irq)->affinity);
+               cpumask_setall(irq_get_affinity_mask(irq));
 #endif
                /* Clear the interrupt information */
                iosapic_intr_info[irq].dest = 0;
 
 void set_irq_affinity_info (unsigned int irq, int hwid, int redir)
 {
        if (irq < NR_IRQS) {
-               cpumask_copy(irq_get_irq_data(irq)->affinity,
+               cpumask_copy(irq_get_affinity_mask(irq),
                             cpumask_of(cpu_logical_id(hwid)));
                irq_redir[irq] = (char) (redir & 0xff);
        }
                if (irqd_is_per_cpu(data))
                        continue;
 
-               if (cpumask_any_and(data->affinity, cpu_online_mask)
-                   >= nr_cpu_ids) {
+               if (cpumask_any_and(irq_data_get_affinity_mask(data),
+                                   cpu_online_mask) >= nr_cpu_ids) {
                        /*
                         * Save it for phase 2 processing
                         */
 
        msg.data = data;
 
        pci_write_msi_msg(irq, &msg);
-       cpumask_copy(idata->affinity, cpumask_of(cpu));
+       cpumask_copy(irq_data_get_affinity_mask(idata), cpumask_of(cpu));
 
        return 0;
 }
        msg.address_lo |= MSI_ADDR_DEST_ID_CPU(cpu_physical_id(cpu));
 
        dmar_msi_write(irq, &msg);
-       cpumask_copy(data->affinity, mask);
+       cpumask_copy(irq_data_get_affinity_mask(data), mask);
 
        return 0;
 }
 
        msg.address_lo = (u32)(bus_addr & 0x00000000ffffffff);
 
        pci_write_msi_msg(irq, &msg);
-       cpumask_copy(data->affinity, cpu_mask);
+       cpumask_copy(irq_data_get_affinity_mask(data), cpu_mask);
 
        return 0;
 }