dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
 }
 
-void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
+static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
 {
        static const unsigned shifts[] = { 5, 10, 10 };
        int shift;
        return dispc.fifo_size[plane];
 }
 
-void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
+static void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low,
+               u32 high)
 {
        u8 hi_start, hi_end, lo_start, lo_end;
        u32 unit;
 }
 
 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
-               bool ilace, enum omap_channel channel)
+               bool ilace, enum omap_channel channel, bool replication,
+               u32 fifo_low, u32 fifo_high)
 {
        const int maxdownscale = cpu_is_omap34xx() ? 4 : 2;
        bool five_taps = 0;
        unsigned int field_offset = 0;
 
        DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
-               "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d\n",
-               plane, oi->paddr, oi->p_uv_addr, oi->screen_width, oi->pos_x,
-               oi->pos_y, oi->width, oi->height, oi->out_width, oi->out_height,
-               oi->color_mode, oi->rotation, oi->mirror, ilace, channel);
+               "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d "
+               "fifo_low %d fifo high %d\n", plane, oi->paddr, oi->p_uv_addr,
+               oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
+               oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
+               oi->mirror, ilace, channel, replication, fifo_low, fifo_high);
 
        if (oi->paddr == 0)
                return -EINVAL;
 
        dispc_ovl_set_channel_out(plane, channel);
 
+       dispc_ovl_enable_replication(plane, replication);
+       dispc_ovl_set_fifo_threshold(plane, fifo_low, fifo_high);
+
        return 0;
 }
 
 
 
 
 u32 dispc_ovl_get_fifo_size(enum omap_plane plane);
-void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high);
 u32 dispc_ovl_get_burst_size(enum omap_plane plane);
 int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
-               bool ilace, enum omap_channel channel);
+               bool ilace, enum omap_channel channel, bool replication,
+               u32 fifo_low, u32 fifo_high);
 int dispc_ovl_enable(enum omap_plane plane, bool enable);
-void dispc_ovl_enable_replication(enum omap_plane plane, bool enable);
 
 
 void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable);
 
        new_oi.out_height = outh;
        new_oi.paddr = paddr;
 
-       r = dispc_ovl_setup(plane, &new_oi, c->ilace, c->channel);
+       r = dispc_ovl_setup(plane, &new_oi, c->ilace, c->channel,
+               c->replication, c->fifo_low, c->fifo_high);
        if (r) {
                /* this shouldn't happen */
                DSSERR("dispc_ovl_setup failed for ovl %d\n", plane);
                return r;
        }
 
-       dispc_ovl_enable_replication(plane, c->replication);
-
-       dispc_ovl_set_fifo_threshold(plane, c->fifo_low, c->fifo_high);
-
        dispc_ovl_enable(plane, 1);
 
        return 0;