platform/x86/amd/pmf: Add support update p3t limit

P3T (Peak Package Power Limit) is a metric within the SMU controller
that can influence the power limits. Add support from the driver
to update P3T limits accordingly.

Reviewed-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com>
Link: https://lore.kernel.org/r/20231212014705.2017474-8-Shyam-sundar.S-k@amd.com
Signed-off-by: Hans de Goede <hdegoede@redhat.com>

diff --git a/drivers/platform/x86/amd/pmf/pmf.h b/drivers/platform/x86/amd/pmf/pmf.h
index 4da51eb28b6f7ad1354869413ae108300a4411b8..37bf1c701361f24e5ffa8e6235d2814b2660f975 100644 (file)
--- a/drivers/platform/x86/amd/pmf/pmf.h
+++ b/drivers/platform/x86/amd/pmf/pmf.h
@@ -49,6 +49,7 @@
 #define GET_STT_MIN_LIMIT      0x1F
 #define GET_STT_LIMIT_APU      0x20
 #define GET_STT_LIMIT_HS2      0x21
+#define SET_P3T                                0x23 /* P3T: Peak Package Power Limit */
 
 /* OS slider update notification */
 #define DC_BEST_PERF           0
@@ -72,6 +73,7 @@
 #define PMF_POLICY_STT_MIN                                     6
 #define PMF_POLICY_STT_SKINTEMP_APU                            7
 #define PMF_POLICY_STT_SKINTEMP_HS2                            8
+#define PMF_POLICY_P3T                                         38
 
 /* TA macros */
 #define PMF_TA_IF_VERSION_MAJOR                                1
@@ -481,6 +483,7 @@ struct pmf_action_table {
        u32 stt_minlimit;       /* in mW */
        u32 stt_skintemp_apu;   /* in C */
        u32 stt_skintemp_hs2;   /* in C */
+       u32 p3t_limit;          /* in mW */
 };
 
 /* Input conditions */

diff --git a/drivers/platform/x86/amd/pmf/tee-if.c b/drivers/platform/x86/amd/pmf/tee-if.c
index e96db406e91ba164dda456c5948abeeedbfb1ff7..bf8cb98d41ec25f7281963c82655801e18d02340 100644 (file)
--- a/drivers/platform/x86/amd/pmf/tee-if.c
+++ b/drivers/platform/x86/amd/pmf/tee-if.c
@@ -105,6 +105,14 @@ static void amd_pmf_apply_policies(struct amd_pmf_dev *dev, struct ta_pmf_enact_
                                dev->prev_data->stt_skintemp_hs2 = val;
                        }
                        break;
+
+               case PMF_POLICY_P3T:
+                       if (dev->prev_data->p3t_limit != val) {
+                               amd_pmf_send_cmd(dev, SET_P3T, false, val, NULL);
+                               dev_dbg(dev->dev, "update P3T: %u\n", val);
+                               dev->prev_data->p3t_limit = val;
+                       }
+                       break;
                }
        }
 }