case MLX5_CMD_OP_DESTROY_GENERAL_OBJECT:
        case MLX5_CMD_OP_DEALLOC_MEMIC:
        case MLX5_CMD_OP_PAGE_FAULT_RESUME:
+       case MLX5_CMD_OP_QUERY_HOST_PARAMS:
                return MLX5_CMD_STAT_OK;
 
        case MLX5_CMD_OP_QUERY_HCA_CAP:
        MLX5_COMMAND_STR_CASE(QUERY_MODIFY_HEADER_CONTEXT);
        MLX5_COMMAND_STR_CASE(ALLOC_MEMIC);
        MLX5_COMMAND_STR_CASE(DEALLOC_MEMIC);
+       MLX5_COMMAND_STR_CASE(QUERY_HOST_PARAMS);
        default: return "unknown command opcode";
        }
 }
 
 
        mlx5_peer_pf_cleanup(dev);
 }
+
+static int mlx5_query_host_params_context(struct mlx5_core_dev *dev,
+                                         u32 *out, int outlen)
+{
+       u32 in[MLX5_ST_SZ_DW(query_host_params_in)] = {};
+
+       MLX5_SET(query_host_params_in, in, opcode,
+                MLX5_CMD_OP_QUERY_HOST_PARAMS);
+
+       return mlx5_cmd_exec(dev, in, sizeof(in), out, outlen);
+}
+
+int mlx5_query_host_params_num_vfs(struct mlx5_core_dev *dev, int *num_vf)
+{
+       u32 out[MLX5_ST_SZ_DW(query_host_params_out)] = {};
+       int err;
+
+       err = mlx5_query_host_params_context(dev, out, sizeof(out));
+       if (err)
+               return err;
+
+       *num_vf = MLX5_GET(query_host_params_out, out,
+                          host_params_context.host_num_of_vfs);
+       mlx5_core_dbg(dev, "host_num_of_vfs %d\n", *num_vf);
+
+       return 0;
+}
 
 bool mlx5_read_embedded_cpu(struct mlx5_core_dev *dev);
 int mlx5_ec_init(struct mlx5_core_dev *dev);
 void mlx5_ec_cleanup(struct mlx5_core_dev *dev);
+int mlx5_query_host_params_num_vfs(struct mlx5_core_dev *dev, int *num_vf);
 
 #else  /* CONFIG_MLX5_ESWITCH */
 
 mlx5_read_embedded_cpu(struct mlx5_core_dev *dev) { return false; }
 static inline int mlx5_ec_init(struct mlx5_core_dev *dev) { return 0; }
 static inline void mlx5_ec_cleanup(struct mlx5_core_dev *dev) {}
+static inline int
+mlx5_query_host_params_num_vfs(struct mlx5_core_dev *dev, int *num_vf)
+{ return -EOPNOTSUPP; }
 
 #endif /* CONFIG_MLX5_ESWITCH */
 
 
        MLX5_CMD_OP_QUERY_XRQ_DC_PARAMS_ENTRY     = 0x725,
        MLX5_CMD_OP_SET_XRQ_DC_PARAMS_ENTRY       = 0x726,
        MLX5_CMD_OP_QUERY_XRQ_ERROR_PARAMS        = 0x727,
+       MLX5_CMD_OP_QUERY_HOST_PARAMS             = 0x740,
        MLX5_CMD_OP_QUERY_VPORT_STATE             = 0x750,
        MLX5_CMD_OP_MODIFY_VPORT_STATE            = 0x751,
        MLX5_CMD_OP_QUERY_ESW_VPORT_CONTEXT       = 0x752,
        u8         reserved_at_80[0x180];
 };
 
+struct mlx5_ifc_host_params_context_bits {
+       u8         host_number[0x8];
+       u8         reserved_at_8[0x8];
+       u8         host_num_of_vfs[0x10];
+
+       u8         reserved_at_20[0x10];
+       u8         host_pci_bus[0x10];
+
+       u8         reserved_at_40[0x10];
+       u8         host_pci_device[0x10];
+
+       u8         reserved_at_60[0x10];
+       u8         host_pci_function[0x10];
+
+       u8         reserved_at_80[0x180];
+};
+
+struct mlx5_ifc_query_host_params_in_bits {
+       u8         opcode[0x10];
+       u8         reserved_at_10[0x10];
+
+       u8         reserved_at_20[0x10];
+       u8         op_mod[0x10];
+
+       u8         reserved_at_40[0x40];
+};
+
+struct mlx5_ifc_query_host_params_out_bits {
+       u8         status[0x8];
+       u8         reserved_at_8[0x18];
+
+       u8         syndrome[0x20];
+
+       u8         reserved_at_40[0x40];
+
+       struct mlx5_ifc_host_params_context_bits host_params_context;
+
+       u8         reserved_at_280[0x180];
+};
+
 #endif /* MLX5_IFC_H */