arm64/sysreg/tools: Move TRFCR definitions to sysreg

Convert TRFCR to automatic generation. Add separate definitions for ELx
and EL2 as TRFCR_EL1 doesn't have CX. This also mirrors the previous
definition so no code change is required.

Also add TRFCR_EL12 which will start to be used in a later commit.

Unfortunately, to avoid breaking the Perf build with duplicate
definition errors, the tools copy of the sysreg.h header needs to be
updated at the same time rather than the usual second commit. This is
because the generated version of sysreg
(arch/arm64/include/generated/asm/sysreg-defs.h), is currently shared
and tools/ does not have its own copy.

Reviewed-by: Mark Brown <broonie@kernel.org>
Signed-off-by: James Clark <james.clark@arm.com>
Signed-off-by: James Clark <james.clark@linaro.org>
Link: https://lore.kernel.org/r/20250106142446.628923-4-james.clark@linaro.org
Signed-off-by: Marc Zyngier <maz@kernel.org>

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index b8303a83c0bff5fbac56f467a11ec4fc735fa8db..808f65818b9111da60e13815b3b8063dc47128f4 100644 (file)
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -283,8 +283,6 @@
 #define SYS_RGSR_EL1                   sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1                    sys_reg(3, 0, 1, 0, 6)
 
-#define SYS_TRFCR_EL1                  sys_reg(3, 0, 1, 2, 1)
-
 #define SYS_TCR_EL1                    sys_reg(3, 0, 2, 0, 2)
 
 #define SYS_APIAKEYLO_EL1              sys_reg(3, 0, 2, 1, 0)
@@ -519,7 +517,6 @@
 #define SYS_VTTBR_EL2                  sys_reg(3, 4, 2, 1, 0)
 #define SYS_VTCR_EL2                   sys_reg(3, 4, 2, 1, 2)
 
-#define SYS_TRFCR_EL2                  sys_reg(3, 4, 1, 2, 1)
 #define SYS_VNCR_EL2                   sys_reg(3, 4, 2, 2, 0)
 #define SYS_HAFGRTR_EL2                        sys_reg(3, 4, 3, 1, 6)
 #define SYS_SPSR_EL2                   sys_reg(3, 4, 4, 0, 0)
@@ -983,15 +980,6 @@
 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
 #define SYS_MPIDR_SAFE_VAL     (BIT(31))
 
-#define TRFCR_ELx_TS_SHIFT             5
-#define TRFCR_ELx_TS_MASK              ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_VIRTUAL           ((0x1UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_GUEST_PHYSICAL    ((0x2UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_PHYSICAL          ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_EL2_CX                   BIT(3)
-#define TRFCR_ELx_ExTRE                        BIT(1)
-#define TRFCR_ELx_E0TRE                        BIT(0)
-
 /* GIC Hypervisor interface registers */
 /* ICH_MISR_EL2 bit definitions */
 #define ICH_MISR_EOI           (1 << 0)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index b081b54d6d227ed8300a6f129896647316f0b673..c28870251220dac1376939a8bd1ca5a5a0f28ae9 100644 (file)
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -1995,6 +1995,22 @@ Sysreg   CPACR_EL1       3       0       1       0       2
 Fields CPACR_ELx
 EndSysreg
 
+SysregFields TRFCR_ELx
+Res0   63:7
+UnsignedEnum   6:5     TS
+       0b0001  VIRTUAL
+       0b0010  GUEST_PHYSICAL
+       0b0011  PHYSICAL
+EndEnum
+Res0   4:2
+Field  1       ExTRE
+Field  0       E0TRE
+EndSysregFields
+
+Sysreg TRFCR_EL1       3       0       1       2       1
+Fields TRFCR_ELx
+EndSysreg
+
 Sysreg SMPRI_EL1       3       0       1       2       4
 Res0   63:4
 Field  3:0     PRIORITY
@@ -2544,6 +2560,22 @@ Field    1       ICIALLU
 Field  0       ICIALLUIS
 EndSysreg
 
+Sysreg TRFCR_EL2       3       4       1       2       1
+Res0   63:7
+UnsignedEnum   6:5     TS
+       0b0000  USE_TRFCR_EL1_TS
+       0b0001  VIRTUAL
+       0b0010  GUEST_PHYSICAL
+       0b0011  PHYSICAL
+EndEnum
+Res0   4
+Field  3       CX
+Res0   2
+Field  1       E2TRE
+Field  0       E0HTRE
+EndSysreg
+
+
 Sysreg HDFGRTR_EL2     3       4       3       1       4
 Field  63      PMBIDR_EL1
 Field  62      nPMSNEVFR_EL1
@@ -2954,6 +2986,10 @@ Sysreg   ZCR_EL12        3       5       1       2       0
 Fields ZCR_ELx
 EndSysreg
 
+Sysreg TRFCR_EL12      3       5       1       2       1
+Fields TRFCR_ELx
+EndSysreg
+
 Sysreg SMCR_EL12       3       5       1       2       6
 Fields SMCR_ELx
 EndSysreg

diff --git a/tools/arch/arm64/include/asm/sysreg.h b/tools/arch/arm64/include/asm/sysreg.h
index 345e81e0d2b3299ff26cb5b7031cbcdc5142b7cb..150416682e2cbd4570179bc8a7ad0fc6335a6807 100644 (file)
--- a/tools/arch/arm64/include/asm/sysreg.h
+++ b/tools/arch/arm64/include/asm/sysreg.h
@@ -283,8 +283,6 @@
 #define SYS_RGSR_EL1                   sys_reg(3, 0, 1, 0, 5)
 #define SYS_GCR_EL1                    sys_reg(3, 0, 1, 0, 6)
 
-#define SYS_TRFCR_EL1                  sys_reg(3, 0, 1, 2, 1)
-
 #define SYS_TCR_EL1                    sys_reg(3, 0, 2, 0, 2)
 
 #define SYS_APIAKEYLO_EL1              sys_reg(3, 0, 2, 1, 0)
@@ -519,7 +517,6 @@
 #define SYS_VTTBR_EL2                  sys_reg(3, 4, 2, 1, 0)
 #define SYS_VTCR_EL2                   sys_reg(3, 4, 2, 1, 2)
 
-#define SYS_TRFCR_EL2                  sys_reg(3, 4, 1, 2, 1)
 #define SYS_VNCR_EL2                   sys_reg(3, 4, 2, 2, 0)
 #define SYS_HAFGRTR_EL2                        sys_reg(3, 4, 3, 1, 6)
 #define SYS_SPSR_EL2                   sys_reg(3, 4, 4, 0, 0)
@@ -983,15 +980,6 @@
 /* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */
 #define SYS_MPIDR_SAFE_VAL     (BIT(31))
 
-#define TRFCR_ELx_TS_SHIFT             5
-#define TRFCR_ELx_TS_MASK              ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_VIRTUAL           ((0x1UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_GUEST_PHYSICAL    ((0x2UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_ELx_TS_PHYSICAL          ((0x3UL) << TRFCR_ELx_TS_SHIFT)
-#define TRFCR_EL2_CX                   BIT(3)
-#define TRFCR_ELx_ExTRE                        BIT(1)
-#define TRFCR_ELx_E0TRE                        BIT(0)
-
 /* GIC Hypervisor interface registers */
 /* ICH_MISR_EL2 bit definitions */
 #define ICH_MISR_EOI           (1 << 0)