#include "intel_display_power_map.h"
#include "intel_display_power_well.h"
-#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
+#define __LIST_INLINE_ELEMS(__elem_type, ...) \
+ ((__elem_type[]) { __VA_ARGS__ })
+
+#define __LIST(__elems) { \
+ .list = __elems, \
+ .count = ARRAY_SIZE(__elems), \
+}
+
+#define I915_PW_DOMAINS(...) \
+ (const struct i915_power_domain_list) \
+ __LIST(__LIST_INLINE_ELEMS(enum intel_display_power_domain, __VA_ARGS__))
+
+#define I915_DECL_PW_DOMAINS(__name, ...) \
+ static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__)
+
+/* Zero-length list assigns all power domains, a NULL list assigns none. */
+#define I915_PW_DOMAINS_NONE NULL
+#define I915_PW_DOMAINS_ALL /* zero-length list */
+
+
+I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
},
};
-#define I830_PIPES_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc i830_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "pipes",
- .domains = I830_PIPES_POWER_DOMAINS,
+ .domain_list = &i830_pwdoms_pipes,
.ops = &i830_pipes_power_well_ops,
.id = DISP_PW_ID_NONE,
},
};
-#define HSW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_CRT, /* DDI E */
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc hsw_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = HSW_DISPLAY_POWER_DOMAINS,
+ .domain_list = &hsw_pwdoms_display,
.ops = &hsw_power_well_ops,
.has_vga = true,
.id = HSW_DISP_PW_GLOBAL,
},
};
-#define BDW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_CRT, /* DDI E */
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc bdw_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = BDW_DISPLAY_POWER_DOMAINS,
+ .domain_list = &bdw_pwdoms_display,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
},
};
-#define VLV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_PORT_CRT,
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_CRT,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc vlv_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = VLV_DISPLAY_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_display,
.ops = &vlv_display_power_well_ops,
.id = VLV_DISP_PW_DISP2D,
{
},
}, {
.name = "dpio-tx-b-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "dpio-tx-b-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "dpio-tx-c-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "dpio-tx-c-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "dpio-common",
- .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_cmn_bc,
.ops = &vlv_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
},
};
-#define CHV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(chv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc chv_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
* power wells don't actually exist. Pipe A power well is
* required for any pipe to work.
*/
- .domains = CHV_DISPLAY_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_display,
.ops = &chv_pipe_power_well_ops,
.id = DISP_PW_ID_NONE,
}, {
.name = "dpio-common-bc",
- .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_dpio_cmn_bc,
.ops = &chv_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
},
}, {
.name = "dpio-common-d",
- .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_dpio_cmn_d,
.ops = &chv_dpio_cmn_power_well_ops,
.id = CHV_DISP_PW_DPIO_CMN_D,
{
},
};
-#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D
+
+I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
+ SKL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
+ SKL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
+ POWER_DOMAIN_PORT_DDI_IO_A,
+ POWER_DOMAIN_PORT_DDI_IO_E,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
+ POWER_DOMAIN_PORT_DDI_IO_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
+ POWER_DOMAIN_PORT_DDI_IO_C,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
+ POWER_DOMAIN_PORT_DDI_IO_D,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc skl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
}, {
.name = "MISC_IO",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.id = SKL_DISP_PW_MISC_IO,
},
}, {
.name = "DC_off",
- .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
},
}, {
.name = "DDI_IO_A_E",
- .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_a_e,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_B",
- .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_C",
- .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_D",
- .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_d,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
};
-#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
+
+I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
+ BXT_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
+ BXT_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc bxt_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
},
}, {
.name = "DC_off",
- .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
},
}, {
.name = "dpio-common-a",
- .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dpio_cmn_a,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DISP_PW_DPIO_CMN_A,
{
},
}, {
.name = "dpio-common-bc",
- .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dpio_cmn_bc,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
},
};
-#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
-
-#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
+ GLK_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
+ GLK_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc glk_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
},
}, {
.name = "DC_off",
- .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
},
}, {
.name = "dpio-common-a",
- .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_a,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DISP_PW_DPIO_CMN_A,
{
},
}, {
.name = "dpio-common-b",
- .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_b,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
},
}, {
.name = "dpio-common-c",
- .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_c,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = GLK_DISP_PW_DPIO_CMN_C,
{
},
}, {
.name = "AUX_A",
- .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_a,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_B",
- .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_C",
- .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_A",
- .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_a,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_B",
- .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_C",
- .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
* - DDI_A
* - FBC
*/
-#define ICL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
+ ICL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/* VDSC/joining */
-#define ICL_PW_3_POWER_DOMAINS ( \
- ICL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_F) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_E) | \
- BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_E) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_F) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_3_POWER_DOMAINS \
+ ICL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_PORT_DDI_LANES_F, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D, \
+ POWER_DOMAIN_AUX_E, \
+ POWER_DOMAIN_AUX_F, \
+ POWER_DOMAIN_AUX_TBT_C, \
+ POWER_DOMAIN_AUX_TBT_D, \
+ POWER_DOMAIN_AUX_TBT_E, \
+ POWER_DOMAIN_AUX_TBT_F
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
+ ICL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* - transcoder WD
* - KVMR (HW control)
*/
-#define ICL_PW_2_POWER_DOMAINS ( \
- ICL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_2_POWER_DOMAINS \
+ ICL_PW_3_POWER_DOMAINS, \
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
+ ICL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* - KVMR (HW control)
*/
-#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- ICL_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_DC_OFF) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
-#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
-#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
-#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D)
-#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E)
-#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_F)
-
-#define ICL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A))
-
-#define ICL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
-#define ICL_AUX_C_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
-#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
-#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
-#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
-#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_C)
-#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_D)
-#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_E)
-#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_F)
+I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
+ ICL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_DC_OFF,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F);
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
},
}, {
.name = "DC_off",
- .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = ICL_PW_2_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
},
}, {
.name = "PW_3",
- .domains = ICL_PW_3_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_D",
- .domains = ICL_DDI_IO_D_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_d,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_E",
- .domains = ICL_DDI_IO_E_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_e,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_F",
- .domains = ICL_DDI_IO_F_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_f,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_C",
- .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_D",
- .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_d,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_E",
- .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_e,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_F",
- .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_f,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT1",
- .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT2",
- .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT3",
- .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT4",
- .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "PW_4",
- .domains = ICL_PW_4_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
},
};
-#define TGL_PW_5_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_4_POWER_DOMAINS ( \
- TGL_PW_5_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_2_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
-#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
-#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
-
-#define TGL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A))
-#define TGL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
-#define TGL_AUX_C_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
-
-#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
-#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
-#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
-
-#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
-#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
-#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
-
-#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
+#define TGL_PW_5_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
+ TGL_PW_5_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define TGL_PW_4_POWER_DOMAINS \
+ TGL_PW_5_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
+ TGL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define TGL_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC5, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC6, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_USBC5, \
+ POWER_DOMAIN_AUX_USBC6, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4, \
+ POWER_DOMAIN_AUX_TBT5, \
+ POWER_DOMAIN_AUX_TBT6
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_USBC5,
+ POWER_DOMAIN_AUX_USBC6,
+ POWER_DOMAIN_AUX_TBT1,
+ POWER_DOMAIN_AUX_TBT2,
+ POWER_DOMAIN_AUX_TBT3,
+ POWER_DOMAIN_AUX_TBT4,
+ POWER_DOMAIN_AUX_TBT5,
+ POWER_DOMAIN_AUX_TBT6,
+ POWER_DOMAIN_TC_COLD_OFF);
static const struct i915_power_well_desc tgl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
},
}, {
.name = "DC_off",
- .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = TGL_PW_2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
},
}, {
.name = "PW_3",
- .domains = TGL_PW_3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_TC3",
- .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc3,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_TC4",
- .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc4,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_TC5",
- .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc5,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_TC6",
- .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc6,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "TC_cold_off",
- .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_tc_cold_off,
.ops = &tgl_tc_cold_off_ops,
.id = TGL_DISP_PW_TC_COLD_OFF,
}, {
.name = "AUX_A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_USBC3",
- .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_USBC4",
- .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_USBC5",
- .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc5,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_USBC6",
- .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc6,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT1",
- .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT2",
- .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT3",
- .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT4",
- .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT5",
- .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt5,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT6",
- .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt6,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "PW_4",
- .domains = TGL_PW_4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "PW_5",
- .domains = TGL_PW_5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_5,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
},
};
-#define RKL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define RKL_PW_3_POWER_DOMAINS ( \
- RKL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define RKL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
+
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
+ RKL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define RKL_PW_3_POWER_DOMAINS \
+ RKL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
+
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
+ RKL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* There is no PW_2/PG_2 on RKL.
* - top-level GTC (DDI-level GTC is in the well associated with the DDI)
*/
-#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- RKL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
+ RKL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc rkl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
},
}, {
.name = "DC_off",
- .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_3",
- .domains = RKL_PW_3_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
},
}, {
.name = "PW_4",
- .domains = RKL_PW_4_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
/*
* DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
*/
-#define DG1_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define DG1_PW_2_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define DG1_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
+
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc dg1_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
},
}, {
.name = "DC_off",
- .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = DG1_PW_2_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
},
}, {
.name = "PW_3",
- .domains = DG1_PW_3_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "PW_4",
- .domains = TGL_PW_4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "PW_5",
- .domains = TGL_PW_5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_5,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
* to top. This allows pipes to be power gated independently.
*/
-#define XELPD_PW_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_2_POWER_DOMAINS ( \
- XELPD_PW_B_POWER_DOMAINS | \
- XELPD_PW_C_POWER_DOMAINS | \
- XELPD_PW_D_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define XELPD_PW_D_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
+ XELPD_PW_D_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_C_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
+ XELPD_PW_C_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_B_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
+ XELPD_PW_B_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_2_POWER_DOMAINS \
+ XELPD_PW_B_POWER_DOMAINS, \
+ XELPD_PW_C_POWER_DOMAINS, \
+ XELPD_PW_D_POWER_DOMAINS, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D_XELPD, \
+ POWER_DOMAIN_AUX_E_XELPD, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
+ XELPD_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* XELPD PW_1/PG_1 domains (under HW/DMC control):
* - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
*/
-#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- XELPD_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
-#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
-#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
-
-#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
-
-#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
-#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
-#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
+ XELPD_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
static const struct i915_power_well_desc xelpd_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
},
}, {
.name = "DC_off",
- .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = XELPD_PW_2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.has_fuses = true,
},
}, {
.name = "PW_A",
- .domains = XELPD_PW_A_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_a,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_A),
.has_fuses = true,
},
}, {
.name = "PW_B",
- .domains = XELPD_PW_B_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_b,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
},
}, {
.name = "PW_C",
- .domains = XELPD_PW_C_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_c,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
},
}, {
.name = "PW_D",
- .domains = XELPD_PW_D_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_d,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_D),
.has_fuses = true,
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_D_XELPD",
- .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_d_xelpd,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_E_XELPD",
- .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_e_xelpd,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_TC1",
- .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_TC2",
- .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_TC3",
- .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc3,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "DDI_IO_TC4",
- .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc4,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
}
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_D_XELPD",
- .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_d_xelpd,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_E_XELPD",
- .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_e_xelpd,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_USBC1",
- .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_USBC2",
- .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_USBC3",
- .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc3,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_USBC4",
- .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc4,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
},
}, {
.name = "AUX_TBT1",
- .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT2",
- .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT3",
- .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
}, {
.name = "AUX_TBT4",
- .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
},
};
+static void init_power_well_domains(const struct i915_power_well_desc *desc,
+ struct i915_power_well *power_well)
+{
+ int j;
+
+ if (!desc->domain_list)
+ return;
+
+ if (desc->domain_list->count == 0) {
+ power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
+
+ return;
+ }
+
+ for (j = 0; j < desc->domain_list->count; j++)
+ power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
+}
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc *power_well_descs,
if (BIT_ULL(id) & skip_mask)
continue;
- power_domains->power_wells[plt_idx++].desc =
+ power_domains->power_wells[plt_idx].desc =
&power_well_descs[i];
+ init_power_well_domains(&power_well_descs[i], &power_domains->power_wells[plt_idx]);
+
+ plt_idx++;
+
if (id == DISP_PW_ID_NONE)
continue;
projects / users / hch / xfs.git / commitdiff