drm/amdgpu/mes: add API for legacy queue reset

Add API for resetting kernel queues.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
index 1b1e94b5b9777604c234996a6b02ad1b8a9bf28b..b2a9df20291347018775b4cc0cde27fd5f1ef878 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.c
@@ -819,6 +819,30 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
        return r;
 }
 
+int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
+                                 struct amdgpu_ring *ring,
+                                 unsigned int vmid)
+{
+       struct mes_reset_legacy_queue_input queue_input;
+       int r;
+
+       memset(&queue_input, 0, sizeof(queue_input));
+
+       queue_input.queue_type = ring->funcs->type;
+       queue_input.doorbell_offset = ring->doorbell_index;
+       queue_input.pipe_id = ring->pipe;
+       queue_input.queue_id = ring->queue;
+       queue_input.mqd_addr = amdgpu_bo_gpu_offset(ring->mqd_obj);
+       queue_input.wptr_addr = ring->wptr_gpu_addr;
+       queue_input.vmid = vmid;
+
+       r = adev->mes.funcs->reset_legacy_queue(&adev->mes, &queue_input);
+       if (r)
+               DRM_ERROR("failed to reset legacy queue\n");
+
+       return r;
+}
+
 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg)
 {
        struct mes_misc_op_input op_input;

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
index 2d659c612f033f1a124ef1d1e8880b77c1a05285..174283a0fc07e9485733b27097ac831220430714 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_mes.h
@@ -279,6 +279,16 @@ struct mes_resume_gang_input {
        uint64_t        gang_context_addr;
 };
 
+struct mes_reset_legacy_queue_input {
+       uint32_t                           queue_type;
+       uint32_t                           doorbell_offset;
+       uint32_t                           pipe_id;
+       uint32_t                           queue_id;
+       uint64_t                           mqd_addr;
+       uint64_t                           wptr_addr;
+       uint32_t                           vmid;
+};
+
 enum mes_misc_opcode {
        MES_MISC_OP_WRITE_REG,
        MES_MISC_OP_READ_REG,
@@ -347,6 +357,9 @@ struct amdgpu_mes_funcs {
 
        int (*misc_op)(struct amdgpu_mes *mes,
                       struct mes_misc_op_input *input);
+
+       int (*reset_legacy_queue)(struct amdgpu_mes *mes,
+                                 struct mes_reset_legacy_queue_input *input);
 };
 
 #define amdgpu_mes_kiq_hw_init(adev) (adev)->mes.kiq_hw_init((adev))
@@ -381,6 +394,9 @@ int amdgpu_mes_unmap_legacy_queue(struct amdgpu_device *adev,
                                  struct amdgpu_ring *ring,
                                  enum amdgpu_unmap_queues_action action,
                                  u64 gpu_addr, u64 seq);
+int amdgpu_mes_reset_legacy_queue(struct amdgpu_device *adev,
+                                 struct amdgpu_ring *ring,
+                                 unsigned int vmid);
 
 uint32_t amdgpu_mes_rreg(struct amdgpu_device *adev, uint32_t reg);
 int amdgpu_mes_wreg(struct amdgpu_device *adev,