#define have_field(S, F) have_field1((S), FLD_O_##F)
#define get_field(S, F) get_field1((S), FLD_O_##F, FLD_C_##F)
-static bool have_field1(const DisasFields *f, enum DisasFieldIndexO c)
+static bool have_field1(const DisasContext *s, enum DisasFieldIndexO c)
{
- return (f->presentO >> c) & 1;
+ return (s->fields->presentO >> c) & 1;
}
-static int get_field1(const DisasFields *f, enum DisasFieldIndexO o,
+static int get_field1(const DisasContext *s, enum DisasFieldIndexO o,
enum DisasFieldIndexC c)
{
- assert(have_field1(f, o));
- return f->c[c];
+ assert(have_field1(s, o));
+ return s->fields->c[c];
}
/* Describe the layout of each field in each format. */
static void help_l2_shift(DisasContext *s, DisasOps *o, int mask)
{
- int b2 = get_field(s->fields, b2);
- int d2 = get_field(s->fields, d2);
+ int b2 = get_field(s, b2);
+ int d2 = get_field(s, d2);
if (b2 == 0) {
o->in2 = tcg_const_i64(d2 & mask);
static DisasJumpType op_basi(DisasContext *s, DisasOps *o)
{
pc_to_link_info(o->out, s, s->pc_tmp);
- return help_goto_direct(s, s->base.pc_next + 2 * get_field(s->fields, i2));
+ return help_goto_direct(s, s->base.pc_next + 2 * get_field(s, i2));
}
static DisasJumpType op_bc(DisasContext *s, DisasOps *o)
{
- int m1 = get_field(s->fields, m1);
- bool is_imm = have_field(s->fields, i2);
- int imm = is_imm ? get_field(s->fields, i2) : 0;
+ int m1 = get_field(s, m1);
+ bool is_imm = have_field(s, i2);
+ int imm = is_imm ? get_field(s, i2) : 0;
DisasCompare c;
/* BCR with R2 = 0 causes no branching */
- if (have_field(s->fields, r2) && get_field(s->fields, r2) == 0) {
+ if (have_field(s, r2) && get_field(s, r2) == 0) {
if (m1 == 14) {
/* Perform serialization */
/* FIXME: check for fast-BCR-serialization facility */
static DisasJumpType op_bct32(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- bool is_imm = have_field(s->fields, i2);
- int imm = is_imm ? get_field(s->fields, i2) : 0;
+ int r1 = get_field(s, r1);
+ bool is_imm = have_field(s, i2);
+ int imm = is_imm ? get_field(s, i2) : 0;
DisasCompare c;
TCGv_i64 t;
static DisasJumpType op_bcth(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int imm = get_field(s->fields, i2);
+ int r1 = get_field(s, r1);
+ int imm = get_field(s, i2);
DisasCompare c;
TCGv_i64 t;
static DisasJumpType op_bct64(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- bool is_imm = have_field(s->fields, i2);
- int imm = is_imm ? get_field(s->fields, i2) : 0;
+ int r1 = get_field(s, r1);
+ bool is_imm = have_field(s, i2);
+ int imm = is_imm ? get_field(s, i2) : 0;
DisasCompare c;
c.cond = TCG_COND_NE;
static DisasJumpType op_bx32(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
- bool is_imm = have_field(s->fields, i2);
- int imm = is_imm ? get_field(s->fields, i2) : 0;
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
+ bool is_imm = have_field(s, i2);
+ int imm = is_imm ? get_field(s, i2) : 0;
DisasCompare c;
TCGv_i64 t;
static DisasJumpType op_bx64(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
- bool is_imm = have_field(s->fields, i2);
- int imm = is_imm ? get_field(s->fields, i2) : 0;
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
+ bool is_imm = have_field(s, i2);
+ int imm = is_imm ? get_field(s, i2) : 0;
DisasCompare c;
c.cond = (s->insn->data ? TCG_COND_LE : TCG_COND_GT);
static DisasJumpType op_cj(DisasContext *s, DisasOps *o)
{
- int imm, m3 = get_field(s->fields, m3);
+ int imm, m3 = get_field(s, m3);
bool is_imm;
DisasCompare c;
c.u.s64.a = o->in1;
c.u.s64.b = o->in2;
- is_imm = have_field(s->fields, i4);
+ is_imm = have_field(s, i4);
if (is_imm) {
- imm = get_field(s->fields, i4);
+ imm = get_field(s, i4);
} else {
imm = 0;
- o->out = get_address(s, 0, get_field(s->fields, b4),
- get_field(s->fields, d4));
+ o->out = get_address(s, 0, get_field(s, b4),
+ get_field(s, d4));
}
return help_branch(s, &c, is_imm, imm, o->out);
bool m4_with_fpe)
{
const bool fpe = s390_has_feat(S390_FEAT_FLOATING_POINT_EXT);
- uint8_t m3 = get_field(s->fields, m3);
- uint8_t m4 = get_field(s->fields, m4);
+ uint8_t m3 = get_field(s, m3);
+ uint8_t m4 = get_field(s, m4);
/* m3 field was introduced with FPE */
if (!fpe && m3_with_fpe) {
static DisasJumpType op_cksm(DisasContext *s, DisasOps *o)
{
- int r2 = get_field(s->fields, r2);
+ int r2 = get_field(s, r2);
TCGv_i64 len = tcg_temp_new_i64();
gen_helper_cksm(len, cpu_env, o->in1, o->in2, regs[r2 + 1]);
static DisasJumpType op_clc(DisasContext *s, DisasOps *o)
{
- int l = get_field(s->fields, l1);
+ int l = get_field(s, l1);
TCGv_i32 vl;
switch (l + 1) {
static DisasJumpType op_clcl(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r2 = get_field(s->fields, r2);
+ int r1 = get_field(s, r1);
+ int r2 = get_field(s, r2);
TCGv_i32 t1, t2;
/* r1 and r2 must be even. */
static DisasJumpType op_clcle(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
TCGv_i32 t1, t3;
/* r1 and r3 must be even. */
static DisasJumpType op_clclu(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
TCGv_i32 t1, t3;
/* r1 and r3 must be even. */
static DisasJumpType op_clm(DisasContext *s, DisasOps *o)
{
- TCGv_i32 m3 = tcg_const_i32(get_field(s->fields, m3));
+ TCGv_i32 m3 = tcg_const_i32(get_field(s, m3));
TCGv_i32 t1 = tcg_temp_new_i32();
tcg_gen_extrl_i64_i32(t1, o->in1);
gen_helper_clm(cc_op, cpu_env, t1, m3, o->in2);
static DisasJumpType op_cs(DisasContext *s, DisasOps *o)
{
- int d2 = get_field(s->fields, d2);
- int b2 = get_field(s->fields, b2);
+ int d2 = get_field(s, d2);
+ int b2 = get_field(s, b2);
TCGv_i64 addr, cc;
/* Note that in1 = R3 (new value) and
static DisasJumpType op_cdsg(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
- int d2 = get_field(s->fields, d2);
- int b2 = get_field(s->fields, b2);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
+ int d2 = get_field(s, d2);
+ int b2 = get_field(s, b2);
DisasJumpType ret = DISAS_NEXT;
TCGv_i64 addr;
TCGv_i32 t_r1, t_r3;
static DisasJumpType op_csst(DisasContext *s, DisasOps *o)
{
- int r3 = get_field(s->fields, r3);
+ int r3 = get_field(s, r3);
TCGv_i32 t_r3 = tcg_const_i32(r3);
if (tb_cflags(s->base.tb) & CF_PARALLEL) {
static DisasJumpType op_ct(DisasContext *s, DisasOps *o)
{
- int m3 = get_field(s->fields, m3);
+ int m3 = get_field(s, m3);
TCGLabel *lab = gen_new_label();
TCGCond c;
static DisasJumpType op_cuXX(DisasContext *s, DisasOps *o)
{
- int m3 = get_field(s->fields, m3);
- int r1 = get_field(s->fields, r1);
- int r2 = get_field(s->fields, r2);
+ int m3 = get_field(s, m3);
+ int r1 = get_field(s, r1);
+ int r2 = get_field(s, r2);
TCGv_i32 tr1, tr2, chk;
/* R1 and R2 must both be even. */
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_diag(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
- TCGv_i32 func_code = tcg_const_i32(get_field(s->fields, i2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 func_code = tcg_const_i32(get_field(s, i2));
gen_helper_diag(cpu_env, r1, r3, func_code);
static DisasJumpType op_ear(DisasContext *s, DisasOps *o)
{
- int r2 = get_field(s->fields, r2);
+ int r2 = get_field(s, r2);
tcg_gen_ld32u_i64(o->out, cpu_env, offsetof(CPUS390XState, aregs[r2]));
return DISAS_NEXT;
}
static DisasJumpType op_epsw(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r2 = get_field(s->fields, r2);
+ int r1 = get_field(s, r1);
+ int r2 = get_field(s, r2);
TCGv_i64 t = tcg_temp_new_i64();
/* Note the "subsequently" in the PoO, which implies a defined result
static DisasJumpType op_ex(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
TCGv_i32 ilen;
TCGv_i64 v1;
static DisasJumpType op_icm(DisasContext *s, DisasOps *o)
{
- int m3 = get_field(s->fields, m3);
+ int m3 = get_field(s, m3);
int pos, len, base = s->insn->data;
TCGv_i64 tmp = tcg_temp_new_i64();
uint64_t ccm;
TCGv_i32 m4;
if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
- m4 = tcg_const_i32(get_field(s->fields, m4));
+ m4 = tcg_const_i32(get_field(s, m4));
} else {
m4 = tcg_const_i32(0);
}
TCGv_i32 m4;
if (s390_has_feat(S390_FEAT_LOCAL_TLB_CLEARING)) {
- m4 = tcg_const_i32(get_field(s->fields, m4));
+ m4 = tcg_const_i32(get_field(s, m4));
} else {
m4 = tcg_const_i32(0);
}
static DisasJumpType op_msa(DisasContext *s, DisasOps *o)
{
- int r1 = have_field(s->fields, r1) ? get_field(s->fields, r1) : 0;
- int r2 = have_field(s->fields, r2) ? get_field(s->fields, r2) : 0;
- int r3 = have_field(s->fields, r3) ? get_field(s->fields, r3) : 0;
+ int r1 = have_field(s, r1) ? get_field(s, r1) : 0;
+ int r2 = have_field(s, r2) ? get_field(s, r2) : 0;
+ int r3 = have_field(s, r3) ? get_field(s, r3) : 0;
TCGv_i32 t_r1, t_r2, t_r3, type;
switch (s->insn->data) {
static DisasJumpType op_lat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
- store_reg32_i64(get_field(s->fields, r1), o->in2);
+ store_reg32_i64(get_field(s, r1), o->in2);
/* The value is stored even in case of trap. */
tcg_gen_brcondi_i64(TCG_COND_NE, o->in2, 0, lab);
gen_trap(s);
static DisasJumpType op_lfhat(DisasContext *s, DisasOps *o)
{
TCGLabel *lab = gen_new_label();
- store_reg32h_i64(get_field(s->fields, r1), o->in2);
+ store_reg32h_i64(get_field(s, r1), o->in2);
/* The value is stored even in case of trap. */
tcg_gen_brcondi_i64(TCG_COND_NE, o->in2, 0, lab);
gen_trap(s);
{
DisasCompare c;
- disas_jcc(s, &c, get_field(s->fields, m3));
+ disas_jcc(s, &c, get_field(s, m3));
if (c.is_64) {
tcg_gen_movcond_i64(c.cond, o->out, c.u.s64.a, c.u.s64.b,
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_lctl(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
gen_helper_lctl(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
static DisasJumpType op_lctlg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
gen_helper_lctlg(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
static DisasJumpType op_lam(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
gen_helper_lam(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
static DisasJumpType op_lm32(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
TCGv_i64 t1, t2;
/* Only one register to read. */
static DisasJumpType op_lmh(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
TCGv_i64 t1, t2;
/* Only one register to read. */
static DisasJumpType op_lm64(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
TCGv_i64 t1, t2;
/* Only one register to read. */
}
/* In a serial context, perform the two loads ... */
- a1 = get_address(s, 0, get_field(s->fields, b1), get_field(s->fields, d1));
- a2 = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
+ a1 = get_address(s, 0, get_field(s, b1), get_field(s, d1));
+ a2 = get_address(s, 0, get_field(s, b2), get_field(s, d2));
tcg_gen_qemu_ld_i64(o->out, a1, get_mem_index(s), mop | MO_ALIGN);
tcg_gen_qemu_ld_i64(o->out2, a2, get_mem_index(s), mop | MO_ALIGN);
tcg_temp_free_i64(a1);
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_lura(DisasContext *s, DisasOps *o)
{
- o->addr1 = get_address(s, 0, get_field(s->fields, r2), 0);
+ o->addr1 = get_address(s, 0, get_field(s, r2), 0);
tcg_gen_qemu_ld_tl(o->out, o->addr1, MMU_REAL_IDX, s->insn->data);
return DISAS_NEXT;
}
static DisasJumpType op_lcbb(DisasContext *s, DisasOps *o)
{
- const int64_t block_size = (1ull << (get_field(s->fields, m3) + 6));
+ const int64_t block_size = (1ull << (get_field(s, m3) + 6));
- if (get_field(s->fields, m3) > 6) {
+ if (get_field(s, m3) > 6) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
static DisasJumpType op_mov2e(DisasContext *s, DisasOps *o)
{
- int b2 = get_field(s->fields, b2);
+ int b2 = get_field(s, b2);
TCGv ar1 = tcg_temp_new_i64();
o->out = o->in2;
static DisasJumpType op_mvc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_mvc(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
return DISAS_NEXT;
static DisasJumpType op_mvcin(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_mvcin(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
return DISAS_NEXT;
static DisasJumpType op_mvcl(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r2 = get_field(s->fields, r2);
+ int r1 = get_field(s, r1);
+ int r2 = get_field(s, r2);
TCGv_i32 t1, t2;
/* r1 and r2 must be even. */
static DisasJumpType op_mvcle(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
TCGv_i32 t1, t3;
/* r1 and r3 must be even. */
static DisasJumpType op_mvclu(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
TCGv_i32 t1, t3;
/* r1 and r3 must be even. */
static DisasJumpType op_mvcos(DisasContext *s, DisasOps *o)
{
- int r3 = get_field(s->fields, r3);
+ int r3 = get_field(s, r3);
gen_helper_mvcos(cc_op, cpu_env, o->addr1, o->in2, regs[r3]);
set_cc_static(s);
return DISAS_NEXT;
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_mvcp(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, l1);
+ int r1 = get_field(s, l1);
gen_helper_mvcp(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
static DisasJumpType op_mvcs(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, l1);
+ int r1 = get_field(s, l1);
gen_helper_mvcs(cc_op, cpu_env, regs[r1], o->addr1, o->in2);
set_cc_static(s);
return DISAS_NEXT;
static DisasJumpType op_mvn(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_mvn(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
return DISAS_NEXT;
static DisasJumpType op_mvo(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_mvo(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
return DISAS_NEXT;
static DisasJumpType op_mvst(DisasContext *s, DisasOps *o)
{
- TCGv_i32 t1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 t2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 t1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 t2 = tcg_const_i32(get_field(s, r2));
gen_helper_mvst(cc_op, cpu_env, t1, t2);
tcg_temp_free_i32(t1);
static DisasJumpType op_mvz(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_mvz(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
return DISAS_NEXT;
static DisasJumpType op_maeb(DisasContext *s, DisasOps *o)
{
- TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
+ TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
gen_helper_maeb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
return DISAS_NEXT;
static DisasJumpType op_madb(DisasContext *s, DisasOps *o)
{
- TCGv_i64 r3 = load_freg(get_field(s->fields, r3));
+ TCGv_i64 r3 = load_freg(get_field(s, r3));
gen_helper_madb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
return DISAS_NEXT;
static DisasJumpType op_mseb(DisasContext *s, DisasOps *o)
{
- TCGv_i64 r3 = load_freg32_i64(get_field(s->fields, r3));
+ TCGv_i64 r3 = load_freg32_i64(get_field(s, r3));
gen_helper_mseb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
return DISAS_NEXT;
static DisasJumpType op_msdb(DisasContext *s, DisasOps *o)
{
- TCGv_i64 r3 = load_freg(get_field(s->fields, r3));
+ TCGv_i64 r3 = load_freg(get_field(s, r3));
gen_helper_msdb(o->out, cpu_env, o->in1, o->in2, r3);
tcg_temp_free_i64(r3);
return DISAS_NEXT;
static DisasJumpType op_nc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_nc(cc_op, cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
static DisasJumpType op_oc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_oc(cc_op, cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
static DisasJumpType op_pack(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_pack(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
return DISAS_NEXT;
static DisasJumpType op_pka(DisasContext *s, DisasOps *o)
{
- int l2 = get_field(s->fields, l2) + 1;
+ int l2 = get_field(s, l2) + 1;
TCGv_i32 l;
/* The length must not exceed 32 bytes. */
static DisasJumpType op_pku(DisasContext *s, DisasOps *o)
{
- int l2 = get_field(s->fields, l2) + 1;
+ int l2 = get_field(s, l2) + 1;
TCGv_i32 l;
/* The length must be even and should not exceed 64 bytes. */
static DisasJumpType op_risbg(DisasContext *s, DisasOps *o)
{
- int i3 = get_field(s->fields, i3);
- int i4 = get_field(s->fields, i4);
- int i5 = get_field(s->fields, i5);
+ int i3 = get_field(s, i3);
+ int i4 = get_field(s, i4);
+ int i5 = get_field(s, i5);
int do_zero = i4 & 0x80;
uint64_t mask, imask, pmask;
int pos, len, rot;
static DisasJumpType op_rosbg(DisasContext *s, DisasOps *o)
{
- int i3 = get_field(s->fields, i3);
- int i4 = get_field(s->fields, i4);
- int i5 = get_field(s->fields, i5);
+ int i3 = get_field(s, i3);
+ int i4 = get_field(s, i4);
+ int i5 = get_field(s, i5);
uint64_t mask;
/* If this is a test-only form, arrange to discard the result. */
static DisasJumpType op_sar(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
tcg_gen_st32_i64(o->in2, cpu_env, offsetof(CPUS390XState, aregs[r1]));
return DISAS_NEXT;
}
static DisasJumpType op_sigp(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
gen_helper_sigp(cc_op, cpu_env, o->in2, r1, r3);
set_cc_static(s);
tcg_temp_free_i32(r1);
TCGLabel *lab;
int r1;
- disas_jcc(s, &c, get_field(s->fields, m3));
+ disas_jcc(s, &c, get_field(s, m3));
/* We want to store when the condition is fulfilled, so branch
out when it's not */
}
free_compare(&c);
- r1 = get_field(s->fields, r1);
- a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
+ r1 = get_field(s, r1);
+ a = get_address(s, 0, get_field(s, b2), get_field(s, d2));
switch (s->insn->data) {
case 1: /* STOCG */
tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
static DisasJumpType op_ectg(DisasContext *s, DisasOps *o)
{
- int b1 = get_field(s->fields, b1);
- int d1 = get_field(s->fields, d1);
- int b2 = get_field(s->fields, b2);
- int d2 = get_field(s->fields, d2);
- int r3 = get_field(s->fields, r3);
+ int b1 = get_field(s, b1);
+ int d1 = get_field(s, d1);
+ int b2 = get_field(s, b2);
+ int d2 = get_field(s, d2);
+ int r3 = get_field(s, r3);
TCGv_i64 tmp = tcg_temp_new_i64();
/* fetch all operands first */
static DisasJumpType op_stctg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
gen_helper_stctg(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
static DisasJumpType op_stctl(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
gen_helper_stctl(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
static DisasJumpType op_stnosm(DisasContext *s, DisasOps *o)
{
- uint64_t i2 = get_field(s->fields, i2);
+ uint64_t i2 = get_field(s, i2);
TCGv_i64 t;
/* It is important to do what the instruction name says: STORE THEN.
static DisasJumpType op_stura(DisasContext *s, DisasOps *o)
{
- o->addr1 = get_address(s, 0, get_field(s->fields, r2), 0);
+ o->addr1 = get_address(s, 0, get_field(s, r2), 0);
tcg_gen_qemu_st_tl(o->in1, o->addr1, MMU_REAL_IDX, s->insn->data);
if (s->base.tb->flags & FLAG_MASK_PER) {
static DisasJumpType op_stam(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
gen_helper_stam(cpu_env, r1, o->in2, r3);
tcg_temp_free_i32(r1);
tcg_temp_free_i32(r3);
static DisasJumpType op_stcm(DisasContext *s, DisasOps *o)
{
- int m3 = get_field(s->fields, m3);
+ int m3 = get_field(s, m3);
int pos, base = s->insn->data;
TCGv_i64 tmp = tcg_temp_new_i64();
static DisasJumpType op_stm(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
int size = s->insn->data;
TCGv_i64 tsize = tcg_const_i64(size);
static DisasJumpType op_stmh(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
- int r3 = get_field(s->fields, r3);
+ int r1 = get_field(s, r1);
+ int r3 = get_field(s, r3);
TCGv_i64 t = tcg_temp_new_i64();
TCGv_i64 t4 = tcg_const_i64(4);
TCGv_i64 t32 = tcg_const_i64(32);
static DisasJumpType op_srst(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
gen_helper_srst(cpu_env, r1, r2);
static DisasJumpType op_srstu(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
gen_helper_srstu(cpu_env, r1, r2);
update_psw_addr(s);
update_cc_op(s);
- t = tcg_const_i32(get_field(s->fields, i1) & 0xff);
+ t = tcg_const_i32(get_field(s, i1) & 0xff);
tcg_gen_st_i32(t, cpu_env, offsetof(CPUS390XState, int_svc_code));
tcg_temp_free_i32(t);
static DisasJumpType op_tp(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l1 = tcg_const_i32(get_field(s->fields, l1) + 1);
+ TCGv_i32 l1 = tcg_const_i32(get_field(s, l1) + 1);
gen_helper_tp(cc_op, cpu_env, o->addr1, l1);
tcg_temp_free_i32(l1);
set_cc_static(s);
static DisasJumpType op_tr(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_tr(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
static DisasJumpType op_trt(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_trt(cc_op, cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
static DisasJumpType op_trtr(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_trtr(cc_op, cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
set_cc_static(s);
static DisasJumpType op_trXX(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
TCGv_i32 sizes = tcg_const_i32(s->insn->opc & 3);
TCGv_i32 tst = tcg_temp_new_i32();
- int m3 = get_field(s->fields, m3);
+ int m3 = get_field(s, m3);
if (!s390_has_feat(S390_FEAT_ETF2_ENH)) {
m3 = 0;
static DisasJumpType op_unpk(DisasContext *s, DisasOps *o)
{
- TCGv_i32 l = tcg_const_i32(get_field(s->fields, l1));
+ TCGv_i32 l = tcg_const_i32(get_field(s, l1));
gen_helper_unpk(cpu_env, l, o->addr1, o->in2);
tcg_temp_free_i32(l);
return DISAS_NEXT;
static DisasJumpType op_unpka(DisasContext *s, DisasOps *o)
{
- int l1 = get_field(s->fields, l1) + 1;
+ int l1 = get_field(s, l1) + 1;
TCGv_i32 l;
/* The length must not exceed 32 bytes. */
static DisasJumpType op_unpku(DisasContext *s, DisasOps *o)
{
- int l1 = get_field(s->fields, l1) + 1;
+ int l1 = get_field(s, l1) + 1;
TCGv_i32 l;
/* The length must be even and should not exceed 64 bytes. */
static DisasJumpType op_xc(DisasContext *s, DisasOps *o)
{
- int d1 = get_field(s->fields, d1);
- int d2 = get_field(s->fields, d2);
- int b1 = get_field(s->fields, b1);
- int b2 = get_field(s->fields, b2);
- int l = get_field(s->fields, l1);
+ int d1 = get_field(s, d1);
+ int d2 = get_field(s, d2);
+ int b1 = get_field(s, b1);
+ int b2 = get_field(s, b2);
+ int l = get_field(s, l1);
TCGv_i32 t32;
o->addr1 = get_address(s, 0, b1, d1);
#ifndef CONFIG_USER_ONLY
static DisasJumpType op_clp(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
gen_helper_clp(cpu_env, r2);
tcg_temp_free_i32(r2);
static DisasJumpType op_pcilg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
gen_helper_pcilg(cpu_env, r1, r2);
tcg_temp_free_i32(r1);
static DisasJumpType op_pcistg(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
gen_helper_pcistg(cpu_env, r1, r2);
tcg_temp_free_i32(r1);
static DisasJumpType op_stpcifc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 ar = tcg_const_i32(get_field(s->fields, b2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 ar = tcg_const_i32(get_field(s, b2));
gen_helper_stpcifc(cpu_env, r1, o->addr1, ar);
tcg_temp_free_i32(ar);
static DisasJumpType op_rpcit(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r2 = tcg_const_i32(get_field(s->fields, r2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r2 = tcg_const_i32(get_field(s, r2));
gen_helper_rpcit(cpu_env, r1, r2);
tcg_temp_free_i32(r1);
static DisasJumpType op_pcistb(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 r3 = tcg_const_i32(get_field(s->fields, r3));
- TCGv_i32 ar = tcg_const_i32(get_field(s->fields, b2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 r3 = tcg_const_i32(get_field(s, r3));
+ TCGv_i32 ar = tcg_const_i32(get_field(s, b2));
gen_helper_pcistb(cpu_env, r1, r3, o->addr1, ar);
tcg_temp_free_i32(ar);
static DisasJumpType op_mpcifc(DisasContext *s, DisasOps *o)
{
- TCGv_i32 r1 = tcg_const_i32(get_field(s->fields, r1));
- TCGv_i32 ar = tcg_const_i32(get_field(s->fields, b2));
+ TCGv_i32 r1 = tcg_const_i32(get_field(s, r1));
+ TCGv_i32 ar = tcg_const_i32(get_field(s, b2));
gen_helper_mpcifc(cpu_env, r1, o->addr1, ar);
tcg_temp_free_i32(ar);
static void prep_r1(DisasContext *s, DisasOps *o)
{
- o->out = regs[get_field(s->fields, r1)];
+ o->out = regs[get_field(s, r1)];
o->g_out = true;
}
#define SPEC_prep_r1 0
static void prep_r1_P(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
o->out = regs[r1];
o->out2 = regs[r1 + 1];
o->g_out = o->g_out2 = true;
/* Whenever we need x1 in addition to other inputs, we'll load it to out/out2 */
static void prep_x1(DisasContext *s, DisasOps *o)
{
- o->out = load_freg(get_field(s->fields, r1));
- o->out2 = load_freg(get_field(s->fields, r1) + 2);
+ o->out = load_freg(get_field(s, r1));
+ o->out2 = load_freg(get_field(s, r1) + 2);
}
#define SPEC_prep_x1 SPEC_r1_f128
static void wout_r1(DisasContext *s, DisasOps *o)
{
- store_reg(get_field(s->fields, r1), o->out);
+ store_reg(get_field(s, r1), o->out);
}
#define SPEC_wout_r1 0
static void wout_r1_8(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 8);
}
#define SPEC_wout_r1_8 0
static void wout_r1_16(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
tcg_gen_deposit_i64(regs[r1], regs[r1], o->out, 0, 16);
}
#define SPEC_wout_r1_16 0
static void wout_r1_32(DisasContext *s, DisasOps *o)
{
- store_reg32_i64(get_field(s->fields, r1), o->out);
+ store_reg32_i64(get_field(s, r1), o->out);
}
#define SPEC_wout_r1_32 0
static void wout_r1_32h(DisasContext *s, DisasOps *o)
{
- store_reg32h_i64(get_field(s->fields, r1), o->out);
+ store_reg32h_i64(get_field(s, r1), o->out);
}
#define SPEC_wout_r1_32h 0
static void wout_r1_P32(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
store_reg32_i64(r1, o->out);
store_reg32_i64(r1 + 1, o->out2);
}
static void wout_r1_D32(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
store_reg32_i64(r1 + 1, o->out);
tcg_gen_shri_i64(o->out, o->out, 32);
store_reg32_i64(r1, o->out);
static void wout_r3_P32(DisasContext *s, DisasOps *o)
{
- int r3 = get_field(s->fields, r3);
+ int r3 = get_field(s, r3);
store_reg32_i64(r3, o->out);
store_reg32_i64(r3 + 1, o->out2);
}
static void wout_r3_P64(DisasContext *s, DisasOps *o)
{
- int r3 = get_field(s->fields, r3);
+ int r3 = get_field(s, r3);
store_reg(r3, o->out);
store_reg(r3 + 1, o->out2);
}
static void wout_e1(DisasContext *s, DisasOps *o)
{
- store_freg32_i64(get_field(s->fields, r1), o->out);
+ store_freg32_i64(get_field(s, r1), o->out);
}
#define SPEC_wout_e1 0
static void wout_f1(DisasContext *s, DisasOps *o)
{
- store_freg(get_field(s->fields, r1), o->out);
+ store_freg(get_field(s, r1), o->out);
}
#define SPEC_wout_f1 0
static void wout_x1(DisasContext *s, DisasOps *o)
{
- int f1 = get_field(s->fields, r1);
+ int f1 = get_field(s, r1);
store_freg(f1, o->out);
store_freg(f1 + 2, o->out2);
}
static void wout_cond_r1r2_32(DisasContext *s, DisasOps *o)
{
- if (get_field(s->fields, r1) != get_field(s->fields, r2)) {
- store_reg32_i64(get_field(s->fields, r1), o->out);
+ if (get_field(s, r1) != get_field(s, r2)) {
+ store_reg32_i64(get_field(s, r1), o->out);
}
}
#define SPEC_wout_cond_r1r2_32 0
static void wout_cond_e1e2(DisasContext *s, DisasOps *o)
{
- if (get_field(s->fields, r1) != get_field(s->fields, r2)) {
- store_freg32_i64(get_field(s->fields, r1), o->out);
+ if (get_field(s, r1) != get_field(s, r2)) {
+ store_freg32_i64(get_field(s, r1), o->out);
}
}
#define SPEC_wout_cond_e1e2 0
static void wout_in2_r1(DisasContext *s, DisasOps *o)
{
- store_reg(get_field(s->fields, r1), o->in2);
+ store_reg(get_field(s, r1), o->in2);
}
#define SPEC_wout_in2_r1 0
static void wout_in2_r1_32(DisasContext *s, DisasOps *o)
{
- store_reg32_i64(get_field(s->fields, r1), o->in2);
+ store_reg32_i64(get_field(s, r1), o->in2);
}
#define SPEC_wout_in2_r1_32 0
static void in1_r1(DisasContext *s, DisasOps *o)
{
- o->in1 = load_reg(get_field(s->fields, r1));
+ o->in1 = load_reg(get_field(s, r1));
}
#define SPEC_in1_r1 0
static void in1_r1_o(DisasContext *s, DisasOps *o)
{
- o->in1 = regs[get_field(s->fields, r1)];
+ o->in1 = regs[get_field(s, r1)];
o->g_in1 = true;
}
#define SPEC_in1_r1_o 0
static void in1_r1_32s(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
- tcg_gen_ext32s_i64(o->in1, regs[get_field(s->fields, r1)]);
+ tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r1)]);
}
#define SPEC_in1_r1_32s 0
static void in1_r1_32u(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(o->in1, regs[get_field(s->fields, r1)]);
+ tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r1)]);
}
#define SPEC_in1_r1_32u 0
static void in1_r1_sr32(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
- tcg_gen_shri_i64(o->in1, regs[get_field(s->fields, r1)], 32);
+ tcg_gen_shri_i64(o->in1, regs[get_field(s, r1)], 32);
}
#define SPEC_in1_r1_sr32 0
static void in1_r1p1(DisasContext *s, DisasOps *o)
{
- o->in1 = load_reg(get_field(s->fields, r1) + 1);
+ o->in1 = load_reg(get_field(s, r1) + 1);
}
#define SPEC_in1_r1p1 SPEC_r1_even
static void in1_r1p1_32s(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
- tcg_gen_ext32s_i64(o->in1, regs[get_field(s->fields, r1) + 1]);
+ tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r1) + 1]);
}
#define SPEC_in1_r1p1_32s SPEC_r1_even
static void in1_r1p1_32u(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(o->in1, regs[get_field(s->fields, r1) + 1]);
+ tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r1) + 1]);
}
#define SPEC_in1_r1p1_32u SPEC_r1_even
static void in1_r1_D32(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
o->in1 = tcg_temp_new_i64();
tcg_gen_concat32_i64(o->in1, regs[r1 + 1], regs[r1]);
}
static void in1_r2(DisasContext *s, DisasOps *o)
{
- o->in1 = load_reg(get_field(s->fields, r2));
+ o->in1 = load_reg(get_field(s, r2));
}
#define SPEC_in1_r2 0
static void in1_r2_sr32(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
- tcg_gen_shri_i64(o->in1, regs[get_field(s->fields, r2)], 32);
+ tcg_gen_shri_i64(o->in1, regs[get_field(s, r2)], 32);
}
#define SPEC_in1_r2_sr32 0
static void in1_r3(DisasContext *s, DisasOps *o)
{
- o->in1 = load_reg(get_field(s->fields, r3));
+ o->in1 = load_reg(get_field(s, r3));
}
#define SPEC_in1_r3 0
static void in1_r3_o(DisasContext *s, DisasOps *o)
{
- o->in1 = regs[get_field(s->fields, r3)];
+ o->in1 = regs[get_field(s, r3)];
o->g_in1 = true;
}
#define SPEC_in1_r3_o 0
static void in1_r3_32s(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
- tcg_gen_ext32s_i64(o->in1, regs[get_field(s->fields, r3)]);
+ tcg_gen_ext32s_i64(o->in1, regs[get_field(s, r3)]);
}
#define SPEC_in1_r3_32s 0
static void in1_r3_32u(DisasContext *s, DisasOps *o)
{
o->in1 = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(o->in1, regs[get_field(s->fields, r3)]);
+ tcg_gen_ext32u_i64(o->in1, regs[get_field(s, r3)]);
}
#define SPEC_in1_r3_32u 0
static void in1_r3_D32(DisasContext *s, DisasOps *o)
{
- int r3 = get_field(s->fields, r3);
+ int r3 = get_field(s, r3);
o->in1 = tcg_temp_new_i64();
tcg_gen_concat32_i64(o->in1, regs[r3 + 1], regs[r3]);
}
static void in1_e1(DisasContext *s, DisasOps *o)
{
- o->in1 = load_freg32_i64(get_field(s->fields, r1));
+ o->in1 = load_freg32_i64(get_field(s, r1));
}
#define SPEC_in1_e1 0
static void in1_f1(DisasContext *s, DisasOps *o)
{
- o->in1 = load_freg(get_field(s->fields, r1));
+ o->in1 = load_freg(get_field(s, r1));
}
#define SPEC_in1_f1 0
/* Load the high double word of an extended (128-bit) format FP number */
static void in1_x2h(DisasContext *s, DisasOps *o)
{
- o->in1 = load_freg(get_field(s->fields, r2));
+ o->in1 = load_freg(get_field(s, r2));
}
#define SPEC_in1_x2h SPEC_r2_f128
static void in1_f3(DisasContext *s, DisasOps *o)
{
- o->in1 = load_freg(get_field(s->fields, r3));
+ o->in1 = load_freg(get_field(s, r3));
}
#define SPEC_in1_f3 0
static void in1_la1(DisasContext *s, DisasOps *o)
{
- o->addr1 = get_address(s, 0, get_field(s->fields, b1),
- get_field(s->fields, d1));
+ o->addr1 = get_address(s, 0, get_field(s, b1), get_field(s, d1));
}
#define SPEC_in1_la1 0
static void in1_la2(DisasContext *s, DisasOps *o)
{
- int x2 = have_field(s->fields, x2) ? get_field(s->fields, x2) : 0;
- o->addr1 = get_address(s, x2, get_field(s->fields, b2),
- get_field(s->fields, d2));
+ int x2 = have_field(s, x2) ? get_field(s, x2) : 0;
+ o->addr1 = get_address(s, x2, get_field(s, b2), get_field(s, d2));
}
#define SPEC_in1_la2 0
static void in2_r1_o(DisasContext *s, DisasOps *o)
{
- o->in2 = regs[get_field(s->fields, r1)];
+ o->in2 = regs[get_field(s, r1)];
o->g_in2 = true;
}
#define SPEC_in2_r1_o 0
static void in2_r1_16u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext16u_i64(o->in2, regs[get_field(s->fields, r1)]);
+ tcg_gen_ext16u_i64(o->in2, regs[get_field(s, r1)]);
}
#define SPEC_in2_r1_16u 0
static void in2_r1_32u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(o->in2, regs[get_field(s->fields, r1)]);
+ tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r1)]);
}
#define SPEC_in2_r1_32u 0
static void in2_r1_D32(DisasContext *s, DisasOps *o)
{
- int r1 = get_field(s->fields, r1);
+ int r1 = get_field(s, r1);
o->in2 = tcg_temp_new_i64();
tcg_gen_concat32_i64(o->in2, regs[r1 + 1], regs[r1]);
}
static void in2_r2(DisasContext *s, DisasOps *o)
{
- o->in2 = load_reg(get_field(s->fields, r2));
+ o->in2 = load_reg(get_field(s, r2));
}
#define SPEC_in2_r2 0
static void in2_r2_o(DisasContext *s, DisasOps *o)
{
- o->in2 = regs[get_field(s->fields, r2)];
+ o->in2 = regs[get_field(s, r2)];
o->g_in2 = true;
}
#define SPEC_in2_r2_o 0
static void in2_r2_nz(DisasContext *s, DisasOps *o)
{
- int r2 = get_field(s->fields, r2);
+ int r2 = get_field(s, r2);
if (r2 != 0) {
o->in2 = load_reg(r2);
}
static void in2_r2_8s(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext8s_i64(o->in2, regs[get_field(s->fields, r2)]);
+ tcg_gen_ext8s_i64(o->in2, regs[get_field(s, r2)]);
}
#define SPEC_in2_r2_8s 0
static void in2_r2_8u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext8u_i64(o->in2, regs[get_field(s->fields, r2)]);
+ tcg_gen_ext8u_i64(o->in2, regs[get_field(s, r2)]);
}
#define SPEC_in2_r2_8u 0
static void in2_r2_16s(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext16s_i64(o->in2, regs[get_field(s->fields, r2)]);
+ tcg_gen_ext16s_i64(o->in2, regs[get_field(s, r2)]);
}
#define SPEC_in2_r2_16s 0
static void in2_r2_16u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext16u_i64(o->in2, regs[get_field(s->fields, r2)]);
+ tcg_gen_ext16u_i64(o->in2, regs[get_field(s, r2)]);
}
#define SPEC_in2_r2_16u 0
static void in2_r3(DisasContext *s, DisasOps *o)
{
- o->in2 = load_reg(get_field(s->fields, r3));
+ o->in2 = load_reg(get_field(s, r3));
}
#define SPEC_in2_r3 0
static void in2_r3_sr32(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_shri_i64(o->in2, regs[get_field(s->fields, r3)], 32);
+ tcg_gen_shri_i64(o->in2, regs[get_field(s, r3)], 32);
}
#define SPEC_in2_r3_sr32 0
static void in2_r3_32u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(o->in2, regs[get_field(s->fields, r3)]);
+ tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r3)]);
}
#define SPEC_in2_r3_32u 0
static void in2_r2_32s(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext32s_i64(o->in2, regs[get_field(s->fields, r2)]);
+ tcg_gen_ext32s_i64(o->in2, regs[get_field(s, r2)]);
}
#define SPEC_in2_r2_32s 0
static void in2_r2_32u(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_ext32u_i64(o->in2, regs[get_field(s->fields, r2)]);
+ tcg_gen_ext32u_i64(o->in2, regs[get_field(s, r2)]);
}
#define SPEC_in2_r2_32u 0
static void in2_r2_sr32(DisasContext *s, DisasOps *o)
{
o->in2 = tcg_temp_new_i64();
- tcg_gen_shri_i64(o->in2, regs[get_field(s->fields, r2)], 32);
+ tcg_gen_shri_i64(o->in2, regs[get_field(s, r2)], 32);
}
#define SPEC_in2_r2_sr32 0
static void in2_e2(DisasContext *s, DisasOps *o)
{
- o->in2 = load_freg32_i64(get_field(s->fields, r2));
+ o->in2 = load_freg32_i64(get_field(s, r2));
}
#define SPEC_in2_e2 0
static void in2_f2(DisasContext *s, DisasOps *o)
{
- o->in2 = load_freg(get_field(s->fields, r2));
+ o->in2 = load_freg(get_field(s, r2));
}
#define SPEC_in2_f2 0
/* Load the low double word of an extended (128-bit) format FP number */
static void in2_x2l(DisasContext *s, DisasOps *o)
{
- o->in2 = load_freg(get_field(s->fields, r2) + 2);
+ o->in2 = load_freg(get_field(s, r2) + 2);
}
#define SPEC_in2_x2l SPEC_r2_f128
static void in2_ra2(DisasContext *s, DisasOps *o)
{
- o->in2 = get_address(s, 0, get_field(s->fields, r2), 0);
+ o->in2 = get_address(s, 0, get_field(s, r2), 0);
}
#define SPEC_in2_ra2 0
static void in2_a2(DisasContext *s, DisasOps *o)
{
- int x2 = have_field(s->fields, x2) ? get_field(s->fields, x2) : 0;
- o->in2 = get_address(s, x2, get_field(s->fields, b2),
- get_field(s->fields, d2));
+ int x2 = have_field(s, x2) ? get_field(s, x2) : 0;
+ o->in2 = get_address(s, x2, get_field(s, b2), get_field(s, d2));
}
#define SPEC_in2_a2 0
static void in2_ri2(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64(s->base.pc_next +
- (int64_t)get_field(s->fields, i2) * 2);
+ o->in2 = tcg_const_i64(s->base.pc_next + (int64_t)get_field(s, i2) * 2);
}
#define SPEC_in2_ri2 0
static void in2_i2(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64(get_field(s->fields, i2));
+ o->in2 = tcg_const_i64(get_field(s, i2));
}
#define SPEC_in2_i2 0
static void in2_i2_8u(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64((uint8_t)get_field(s->fields, i2));
+ o->in2 = tcg_const_i64((uint8_t)get_field(s, i2));
}
#define SPEC_in2_i2_8u 0
static void in2_i2_16u(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64((uint16_t)get_field(s->fields, i2));
+ o->in2 = tcg_const_i64((uint16_t)get_field(s, i2));
}
#define SPEC_in2_i2_16u 0
static void in2_i2_32u(DisasContext *s, DisasOps *o)
{
- o->in2 = tcg_const_i64((uint32_t)get_field(s->fields, i2));
+ o->in2 = tcg_const_i64((uint32_t)get_field(s, i2));
}
#define SPEC_in2_i2_32u 0
static void in2_i2_16u_shl(DisasContext *s, DisasOps *o)
{
- uint64_t i2 = (uint16_t)get_field(s->fields, i2);
+ uint64_t i2 = (uint16_t)get_field(s, i2);
o->in2 = tcg_const_i64(i2 << s->insn->data);
}
#define SPEC_in2_i2_16u_shl 0
static void in2_i2_32u_shl(DisasContext *s, DisasOps *o)
{
- uint64_t i2 = (uint32_t)get_field(s->fields, i2);
+ uint64_t i2 = (uint32_t)get_field(s, i2);
o->in2 = tcg_const_i64(i2 << s->insn->data);
}
#define SPEC_in2_i2_32u_shl 0
/* Search for the insn in the table. */
insn = extract_insn(env, s, &f);
+ /* Set up the strutures we use to communicate with the helpers. */
+ s->insn = insn;
+ s->fields = &f;
+
/* Emit insn_start now that we know the ILEN. */
tcg_gen_insn_start(s->base.pc_next, s->cc_op, s->ilen);
if (!(s->base.tb->flags & FLAG_MASK_AFP)) {
uint8_t dxc = 0;
- if ((insn->flags & IF_AFP1) && is_afp_reg(get_field(&f, r1))) {
+ if ((insn->flags & IF_AFP1) && is_afp_reg(get_field(s, r1))) {
dxc = 1;
}
- if ((insn->flags & IF_AFP2) && is_afp_reg(get_field(&f, r2))) {
+ if ((insn->flags & IF_AFP2) && is_afp_reg(get_field(s, r2))) {
dxc = 1;
}
- if ((insn->flags & IF_AFP3) && is_afp_reg(get_field(&f, r3))) {
+ if ((insn->flags & IF_AFP3) && is_afp_reg(get_field(s, r3))) {
dxc = 1;
}
if (insn->flags & IF_BFP) {
/* Check for insn specification exceptions. */
if (insn->spec) {
- if ((insn->spec & SPEC_r1_even && get_field(&f, r1) & 1) ||
- (insn->spec & SPEC_r2_even && get_field(&f, r2) & 1) ||
- (insn->spec & SPEC_r3_even && get_field(&f, r3) & 1) ||
- (insn->spec & SPEC_r1_f128 && !is_fp_pair(get_field(&f, r1))) ||
- (insn->spec & SPEC_r2_f128 && !is_fp_pair(get_field(&f, r2)))) {
+ if ((insn->spec & SPEC_r1_even && get_field(s, r1) & 1) ||
+ (insn->spec & SPEC_r2_even && get_field(s, r2) & 1) ||
+ (insn->spec & SPEC_r3_even && get_field(s, r3) & 1) ||
+ (insn->spec & SPEC_r1_f128 && !is_fp_pair(get_field(s, r1))) ||
+ (insn->spec & SPEC_r2_f128 && !is_fp_pair(get_field(s, r2)))) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
}
- /* Set up the strutures we use to communicate with the helpers. */
- s->insn = insn;
- s->fields = &f;
-
/* Implement the instruction. */
if (insn->help_in1) {
insn->help_in1(s, &o);
static DisasJumpType op_vge(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s->fields, m3);
+ const uint8_t enr = get_field(s, m3);
TCGv_i64 tmp;
if (!valid_vec_element(enr, es)) {
}
tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, get_field(s->fields, v2), enr, es);
+ read_vec_element_i64(tmp, get_field(s, v2), enr, es);
tcg_gen_add_i64(o->addr1, o->addr1, tmp);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ write_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
static DisasJumpType op_vgbm(DisasContext *s, DisasOps *o)
{
- const uint16_t i2 = get_field(s->fields, i2);
+ const uint16_t i2 = get_field(s, i2);
if (i2 == (i2 & 0xff) * 0x0101) {
/*
* Masks for both 64 bit elements of the vector are the same.
* Trust tcg to produce a good constant loading.
*/
- gen_gvec_dup64i(get_field(s->fields, v1),
+ gen_gvec_dup64i(get_field(s, v1),
generate_byte_mask(i2 & 0xff));
} else {
TCGv_i64 t = tcg_temp_new_i64();
tcg_gen_movi_i64(t, generate_byte_mask(i2 >> 8));
- write_vec_element_i64(t, get_field(s->fields, v1), 0, ES_64);
+ write_vec_element_i64(t, get_field(s, v1), 0, ES_64);
tcg_gen_movi_i64(t, generate_byte_mask(i2));
- write_vec_element_i64(t, get_field(s->fields, v1), 1, ES_64);
+ write_vec_element_i64(t, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(t);
}
return DISAS_NEXT;
static DisasJumpType op_vgm(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
const uint8_t bits = NUM_VEC_ELEMENT_BITS(es);
- const uint8_t i2 = get_field(s->fields, i2) & (bits - 1);
- const uint8_t i3 = get_field(s->fields, i3) & (bits - 1);
+ const uint8_t i2 = get_field(s, i2) & (bits - 1);
+ const uint8_t i3 = get_field(s, i3) & (bits - 1);
uint64_t mask = 0;
int i;
}
}
- gen_gvec_dupi(es, get_field(s->fields, v1), mask);
+ gen_gvec_dupi(es, get_field(s, v1), mask);
return DISAS_NEXT;
}
tcg_gen_qemu_ld_i64(t0, o->addr1, get_mem_index(s), MO_TEQ);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
tcg_gen_qemu_ld_i64(t1, o->addr1, get_mem_index(s), MO_TEQ);
- write_vec_element_i64(t0, get_field(s->fields, v1), 0, ES_64);
- write_vec_element_i64(t1, get_field(s->fields, v1), 1, ES_64);
+ write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free(t0);
tcg_temp_free(t1);
return DISAS_NEXT;
static DisasJumpType op_vlr(DisasContext *s, DisasOps *o)
{
- gen_gvec_mov(get_field(s->fields, v1), get_field(s->fields, v2));
+ gen_gvec_mov(get_field(s, v1), get_field(s, v2));
return DISAS_NEXT;
}
static DisasJumpType op_vlrep(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m3);
+ const uint8_t es = get_field(s, m3);
TCGv_i64 tmp;
if (es > ES_64) {
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- gen_gvec_dup_i64(es, get_field(s->fields, v1), tmp);
+ gen_gvec_dup_i64(es, get_field(s, v1), tmp);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
static DisasJumpType op_vle(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s->fields, m3);
+ const uint8_t enr = get_field(s, m3);
TCGv_i64 tmp;
if (!valid_vec_element(enr, es)) {
tmp = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
- write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ write_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
static DisasJumpType op_vlei(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s->fields, m3);
+ const uint8_t enr = get_field(s, m3);
TCGv_i64 tmp;
if (!valid_vec_element(enr, es)) {
return DISAS_NORETURN;
}
- tmp = tcg_const_i64((int16_t)get_field(s->fields, i2));
- write_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ tmp = tcg_const_i64((int16_t)get_field(s, i2));
+ write_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
static DisasJumpType op_vlgv(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
TCGv_ptr ptr;
if (es > ES_64) {
}
/* fast path if we don't need the register content */
- if (!get_field(s->fields, b2)) {
- uint8_t enr = get_field(s->fields, d2) & (NUM_VEC_ELEMENTS(es) - 1);
+ if (!get_field(s, b2)) {
+ uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1);
- read_vec_element_i64(o->out, get_field(s->fields, v3), enr, es);
+ read_vec_element_i64(o->out, get_field(s, v3), enr, es);
return DISAS_NEXT;
}
ptr = tcg_temp_new_ptr();
- get_vec_element_ptr_i64(ptr, get_field(s->fields, v3), o->addr1, es);
+ get_vec_element_ptr_i64(ptr, get_field(s, v3), o->addr1, es);
switch (es) {
case ES_8:
tcg_gen_ld8u_i64(o->out, ptr, 0);
static DisasJumpType op_vllez(DisasContext *s, DisasOps *o)
{
- uint8_t es = get_field(s->fields, m3);
+ uint8_t es = get_field(s, m3);
uint8_t enr;
TCGv_i64 t;
t = tcg_temp_new_i64();
tcg_gen_qemu_ld_i64(t, o->addr1, get_mem_index(s), MO_TE | es);
- zero_vec(get_field(s->fields, v1));
- write_vec_element_i64(t, get_field(s->fields, v1), enr, es);
+ zero_vec(get_field(s, v1));
+ write_vec_element_i64(t, get_field(s, v1), enr, es);
tcg_temp_free_i64(t);
return DISAS_NEXT;
}
static DisasJumpType op_vlm(DisasContext *s, DisasOps *o)
{
- const uint8_t v3 = get_field(s->fields, v3);
- uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v3 = get_field(s, v3);
+ uint8_t v1 = get_field(s, v1);
TCGv_i64 t0, t1;
if (v3 < v1 || (v3 - v1 + 1) > 16) {
static DisasJumpType op_vlbb(DisasContext *s, DisasOps *o)
{
- const int64_t block_size = (1ull << (get_field(s->fields, m3) + 6));
- const int v1_offs = vec_full_reg_offset(get_field(s->fields, v1));
+ const int64_t block_size = (1ull << (get_field(s, m3) + 6));
+ const int v1_offs = vec_full_reg_offset(get_field(s, v1));
TCGv_ptr a0;
TCGv_i64 bytes;
- if (get_field(s->fields, m3) > 6) {
+ if (get_field(s, m3) > 6) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
static DisasJumpType op_vlvg(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
TCGv_ptr ptr;
if (es > ES_64) {
}
/* fast path if we don't need the register content */
- if (!get_field(s->fields, b2)) {
- uint8_t enr = get_field(s->fields, d2) & (NUM_VEC_ELEMENTS(es) - 1);
+ if (!get_field(s, b2)) {
+ uint8_t enr = get_field(s, d2) & (NUM_VEC_ELEMENTS(es) - 1);
- write_vec_element_i64(o->in2, get_field(s->fields, v1), enr, es);
+ write_vec_element_i64(o->in2, get_field(s, v1), enr, es);
return DISAS_NEXT;
}
ptr = tcg_temp_new_ptr();
- get_vec_element_ptr_i64(ptr, get_field(s->fields, v1), o->addr1, es);
+ get_vec_element_ptr_i64(ptr, get_field(s, v1), o->addr1, es);
switch (es) {
case ES_8:
tcg_gen_st8_i64(o->in2, ptr, 0);
static DisasJumpType op_vlvgp(DisasContext *s, DisasOps *o)
{
- write_vec_element_i64(o->in1, get_field(s->fields, v1), 0, ES_64);
- write_vec_element_i64(o->in2, get_field(s->fields, v1), 1, ES_64);
+ write_vec_element_i64(o->in1, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(o->in2, get_field(s, v1), 1, ES_64);
return DISAS_NEXT;
}
static DisasJumpType op_vll(DisasContext *s, DisasOps *o)
{
- const int v1_offs = vec_full_reg_offset(get_field(s->fields, v1));
+ const int v1_offs = vec_full_reg_offset(get_field(s, v1));
TCGv_ptr a0 = tcg_temp_new_ptr();
/* convert highest index into an actual length */
static DisasJumpType op_vmr(DisasContext *s, DisasOps *o)
{
- const uint8_t v1 = get_field(s->fields, v1);
- const uint8_t v2 = get_field(s->fields, v2);
- const uint8_t v3 = get_field(s->fields, v3);
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t v3 = get_field(s, v3);
+ const uint8_t es = get_field(s, m4);
int dst_idx, src_idx;
TCGv_i64 tmp;
static DisasJumpType op_vpk(DisasContext *s, DisasOps *o)
{
- const uint8_t v1 = get_field(s->fields, v1);
- const uint8_t v2 = get_field(s->fields, v2);
- const uint8_t v3 = get_field(s->fields, v3);
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t v3 = get_field(s, v3);
+ const uint8_t es = get_field(s, m4);
static gen_helper_gvec_3 * const vpk[3] = {
gen_helper_gvec_vpk16,
gen_helper_gvec_vpk32,
switch (s->fields->op2) {
case 0x97:
- if (get_field(s->fields, m5) & 0x1) {
+ if (get_field(s, m5) & 0x1) {
gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpks_cc[es - 1]);
set_cc_static(s);
} else {
}
break;
case 0x95:
- if (get_field(s->fields, m5) & 0x1) {
+ if (get_field(s, m5) & 0x1) {
gen_gvec_3_ptr(v1, v2, v3, cpu_env, 0, vpkls_cc[es - 1]);
set_cc_static(s);
} else {
case 0x94:
/* If sources and destination dont't overlap -> fast path */
if (v1 != v2 && v1 != v3) {
- const uint8_t src_es = get_field(s->fields, m4);
+ const uint8_t src_es = get_field(s, m4);
const uint8_t dst_es = src_es - 1;
TCGv_i64 tmp = tcg_temp_new_i64();
int dst_idx, src_idx;
static DisasJumpType op_vperm(DisasContext *s, DisasOps *o)
{
- gen_gvec_4_ool(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), get_field(s->fields, v4),
+ gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
0, gen_helper_gvec_vperm);
return DISAS_NEXT;
}
static DisasJumpType op_vpdi(DisasContext *s, DisasOps *o)
{
- const uint8_t i2 = extract32(get_field(s->fields, m4), 2, 1);
- const uint8_t i3 = extract32(get_field(s->fields, m4), 0, 1);
+ const uint8_t i2 = extract32(get_field(s, m4), 2, 1);
+ const uint8_t i3 = extract32(get_field(s, m4), 0, 1);
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t1 = tcg_temp_new_i64();
- read_vec_element_i64(t0, get_field(s->fields, v2), i2, ES_64);
- read_vec_element_i64(t1, get_field(s->fields, v3), i3, ES_64);
- write_vec_element_i64(t0, get_field(s->fields, v1), 0, ES_64);
- write_vec_element_i64(t1, get_field(s->fields, v1), 1, ES_64);
+ read_vec_element_i64(t0, get_field(s, v2), i2, ES_64);
+ read_vec_element_i64(t1, get_field(s, v3), i3, ES_64);
+ write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(t0);
tcg_temp_free_i64(t1);
return DISAS_NEXT;
static DisasJumpType op_vrep(DisasContext *s, DisasOps *o)
{
- const uint8_t enr = get_field(s->fields, i2);
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t enr = get_field(s, i2);
+ const uint8_t es = get_field(s, m4);
if (es > ES_64 || !valid_vec_element(enr, es)) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- tcg_gen_gvec_dup_mem(es, vec_full_reg_offset(get_field(s->fields, v1)),
- vec_reg_offset(get_field(s->fields, v3), enr, es),
+ tcg_gen_gvec_dup_mem(es, vec_full_reg_offset(get_field(s, v1)),
+ vec_reg_offset(get_field(s, v3), enr, es),
16, 16);
return DISAS_NEXT;
}
static DisasJumpType op_vrepi(DisasContext *s, DisasOps *o)
{
- const int64_t data = (int16_t)get_field(s->fields, i2);
- const uint8_t es = get_field(s->fields, m3);
+ const int64_t data = (int16_t)get_field(s, i2);
+ const uint8_t es = get_field(s, m3);
if (es > ES_64) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_dupi(es, get_field(s->fields, v1), data);
+ gen_gvec_dupi(es, get_field(s, v1), data);
return DISAS_NEXT;
}
static DisasJumpType op_vsce(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s->fields, m3);
+ const uint8_t enr = get_field(s, m3);
TCGv_i64 tmp;
if (!valid_vec_element(enr, es)) {
}
tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, get_field(s->fields, v2), enr, es);
+ read_vec_element_i64(tmp, get_field(s, v2), enr, es);
tcg_gen_add_i64(o->addr1, o->addr1, tmp);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 0);
- read_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ read_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
static DisasJumpType op_vsel(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_4(bitsel, ES_8, get_field(s->fields, v1),
- get_field(s->fields, v4), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_4(bitsel, ES_8, get_field(s, v1),
+ get_field(s, v4), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vseg(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m3);
+ const uint8_t es = get_field(s, m3);
int idx1, idx2;
TCGv_i64 tmp;
}
tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, get_field(s->fields, v2), idx1, es | MO_SIGN);
- write_vec_element_i64(tmp, get_field(s->fields, v1), 0, ES_64);
- read_vec_element_i64(tmp, get_field(s->fields, v2), idx2, es | MO_SIGN);
- write_vec_element_i64(tmp, get_field(s->fields, v1), 1, ES_64);
+ read_vec_element_i64(tmp, get_field(s, v2), idx1, es | MO_SIGN);
+ write_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
+ read_vec_element_i64(tmp, get_field(s, v2), idx2, es | MO_SIGN);
+ write_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
}
/* Probe write access before actually modifying memory */
gen_helper_probe_write_access(cpu_env, o->addr1, tmp);
- read_vec_element_i64(tmp, get_field(s->fields, v1), 0, ES_64);
+ read_vec_element_i64(tmp, get_field(s, v1), 0, ES_64);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
gen_addi_and_wrap_i64(s, o->addr1, o->addr1, 8);
- read_vec_element_i64(tmp, get_field(s->fields, v1), 1, ES_64);
+ read_vec_element_i64(tmp, get_field(s, v1), 1, ES_64);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TEQ);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
static DisasJumpType op_vste(DisasContext *s, DisasOps *o)
{
const uint8_t es = s->insn->data;
- const uint8_t enr = get_field(s->fields, m3);
+ const uint8_t enr = get_field(s, m3);
TCGv_i64 tmp;
if (!valid_vec_element(enr, es)) {
}
tmp = tcg_temp_new_i64();
- read_vec_element_i64(tmp, get_field(s->fields, v1), enr, es);
+ read_vec_element_i64(tmp, get_field(s, v1), enr, es);
tcg_gen_qemu_st_i64(tmp, o->addr1, get_mem_index(s), MO_TE | es);
tcg_temp_free_i64(tmp);
return DISAS_NEXT;
static DisasJumpType op_vstm(DisasContext *s, DisasOps *o)
{
- const uint8_t v3 = get_field(s->fields, v3);
- uint8_t v1 = get_field(s->fields, v1);
+ const uint8_t v3 = get_field(s, v3);
+ uint8_t v1 = get_field(s, v1);
TCGv_i64 tmp;
while (v3 < v1 || (v3 - v1 + 1) > 16) {
static DisasJumpType op_vstl(DisasContext *s, DisasOps *o)
{
- const int v1_offs = vec_full_reg_offset(get_field(s->fields, v1));
+ const int v1_offs = vec_full_reg_offset(get_field(s, v1));
TCGv_ptr a0 = tcg_temp_new_ptr();
/* convert highest index into an actual length */
static DisasJumpType op_vup(DisasContext *s, DisasOps *o)
{
const bool logical = s->fields->op2 == 0xd4 || s->fields->op2 == 0xd5;
- const uint8_t v1 = get_field(s->fields, v1);
- const uint8_t v2 = get_field(s->fields, v2);
- const uint8_t src_es = get_field(s->fields, m3);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t src_es = get_field(s, m3);
const uint8_t dst_es = src_es + 1;
int dst_idx, src_idx;
TCGv_i64 tmp;
static DisasJumpType op_va(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
if (es > ES_128) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
} else if (es == ES_128) {
- gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3));
+ gen_gvec128_3_i64(tcg_gen_add2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
return DISAS_NEXT;
}
- gen_gvec_fn_3(add, es, get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_3(add, es, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vacc(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
static const GVecGen3 g[4] = {
{ .fni8 = gen_acc8_i64, },
{ .fni8 = gen_acc16_i64, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
} else if (es == ES_128) {
- gen_gvec128_3_i64(gen_acc2_i64, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3));
+ gen_gvec128_3_i64(gen_acc2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
return DISAS_NEXT;
}
- gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), &g[es]);
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_vac(DisasContext *s, DisasOps *o)
{
- if (get_field(s->fields, m5) != ES_128) {
+ if (get_field(s, m5) != ES_128) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec128_4_i64(gen_ac2_i64, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3),
- get_field(s->fields, v4));
+ gen_gvec128_4_i64(gen_ac2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3),
+ get_field(s, v4));
return DISAS_NEXT;
}
static DisasJumpType op_vaccc(DisasContext *s, DisasOps *o)
{
- if (get_field(s->fields, m5) != ES_128) {
+ if (get_field(s, m5) != ES_128) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec128_4_i64(gen_accc2_i64, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3),
- get_field(s->fields, v4));
+ gen_gvec128_4_i64(gen_accc2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3),
+ get_field(s, v4));
return DISAS_NEXT;
}
static DisasJumpType op_vn(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_3(and, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_3(and, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vnc(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_3(andc, ES_8, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3));
+ gen_gvec_fn_3(andc, ES_8, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vavg(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
static const GVecGen3 g[4] = {
{ .fno = gen_helper_gvec_vavg8, },
{ .fno = gen_helper_gvec_vavg16, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), &g[es]);
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_vavgl(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
static const GVecGen3 g[4] = {
{ .fno = gen_helper_gvec_vavgl8, },
{ .fno = gen_helper_gvec_vavgl16, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), &g[es]);
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
return DISAS_NEXT;
}
TCGv_i32 sum = tcg_temp_new_i32();
int i;
- read_vec_element_i32(sum, get_field(s->fields, v3), 1, ES_32);
+ read_vec_element_i32(sum, get_field(s, v3), 1, ES_32);
for (i = 0; i < 4; i++) {
- read_vec_element_i32(tmp, get_field(s->fields, v2), i, ES_32);
+ read_vec_element_i32(tmp, get_field(s, v2), i, ES_32);
tcg_gen_add2_i32(tmp, sum, sum, sum, tmp, tmp);
}
- zero_vec(get_field(s->fields, v1));
- write_vec_element_i32(sum, get_field(s->fields, v1), 1, ES_32);
+ zero_vec(get_field(s, v1));
+ write_vec_element_i32(sum, get_field(s, v1), 1, ES_32);
tcg_temp_free_i32(tmp);
tcg_temp_free_i32(sum);
static DisasJumpType op_vec(DisasContext *s, DisasOps *o)
{
- uint8_t es = get_field(s->fields, m3);
+ uint8_t es = get_field(s, m3);
const uint8_t enr = NUM_VEC_ELEMENTS(es) / 2 - 1;
if (es > ES_64) {
o->in1 = tcg_temp_new_i64();
o->in2 = tcg_temp_new_i64();
- read_vec_element_i64(o->in1, get_field(s->fields, v1), enr, es);
- read_vec_element_i64(o->in2, get_field(s->fields, v2), enr, es);
+ read_vec_element_i64(o->in1, get_field(s, v1), enr, es);
+ read_vec_element_i64(o->in2, get_field(s, v2), enr, es);
return DISAS_NEXT;
}
static DisasJumpType op_vc(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
TCGCond cond = s->insn->data;
if (es > ES_64) {
}
tcg_gen_gvec_cmp(cond, es,
- vec_full_reg_offset(get_field(s->fields, v1)),
- vec_full_reg_offset(get_field(s->fields, v2)),
- vec_full_reg_offset(get_field(s->fields, v3)), 16, 16);
- if (get_field(s->fields, m5) & 0x1) {
+ vec_full_reg_offset(get_field(s, v1)),
+ vec_full_reg_offset(get_field(s, v2)),
+ vec_full_reg_offset(get_field(s, v3)), 16, 16);
+ if (get_field(s, m5) & 0x1) {
TCGv_i64 low = tcg_temp_new_i64();
TCGv_i64 high = tcg_temp_new_i64();
- read_vec_element_i64(high, get_field(s->fields, v1), 0, ES_64);
- read_vec_element_i64(low, get_field(s->fields, v1), 1, ES_64);
+ read_vec_element_i64(high, get_field(s, v1), 0, ES_64);
+ read_vec_element_i64(low, get_field(s, v1), 1, ES_64);
gen_op_update2_cc_i64(s, CC_OP_VC, low, high);
tcg_temp_free_i64(low);
static DisasJumpType op_vclz(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m3);
+ const uint8_t es = get_field(s, m3);
static const GVecGen2 g[4] = {
{ .fno = gen_helper_gvec_vclz8, },
{ .fno = gen_helper_gvec_vclz16, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_vctz(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m3);
+ const uint8_t es = get_field(s, m3);
static const GVecGen2 g[4] = {
{ .fno = gen_helper_gvec_vctz8, },
{ .fno = gen_helper_gvec_vctz16, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_vx(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_3(xor, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_3(xor, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vgfm(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
static const GVecGen3 g[4] = {
{ .fno = gen_helper_gvec_vgfm8, },
{ .fno = gen_helper_gvec_vgfm16, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), &g[es]);
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_vgfma(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m5);
+ const uint8_t es = get_field(s, m5);
static const GVecGen4 g[4] = {
{ .fno = gen_helper_gvec_vgfma8, },
{ .fno = gen_helper_gvec_vgfma16, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_4(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), get_field(s->fields, v4), &g[es]);
+ gen_gvec_4(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_vlc(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m3);
+ const uint8_t es = get_field(s, m3);
if (es > ES_64) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_fn_2(neg, es, get_field(s->fields, v1), get_field(s->fields, v2));
+ gen_gvec_fn_2(neg, es, get_field(s, v1), get_field(s, v2));
return DISAS_NEXT;
}
static DisasJumpType op_vlp(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m3);
+ const uint8_t es = get_field(s, m3);
if (es > ES_64) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_fn_2(abs, es, get_field(s->fields, v1), get_field(s->fields, v2));
+ gen_gvec_fn_2(abs, es, get_field(s, v1), get_field(s, v2));
return DISAS_NEXT;
}
static DisasJumpType op_vmx(DisasContext *s, DisasOps *o)
{
- const uint8_t v1 = get_field(s->fields, v1);
- const uint8_t v2 = get_field(s->fields, v2);
- const uint8_t v3 = get_field(s->fields, v3);
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t v3 = get_field(s, v3);
+ const uint8_t es = get_field(s, m4);
if (es > ES_64) {
gen_program_exception(s, PGM_SPECIFICATION);
static DisasJumpType op_vma(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m5);
+ const uint8_t es = get_field(s, m5);
static const GVecGen4 g_vmal[3] = {
{ .fno = gen_helper_gvec_vmal8, },
{ .fno = gen_helper_gvec_vmal16, },
g_assert_not_reached();
}
- gen_gvec_4(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), get_field(s->fields, v4), fn);
+ gen_gvec_4(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4), fn);
return DISAS_NEXT;
}
static DisasJumpType op_vm(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
static const GVecGen3 g_vmh[3] = {
{ .fno = gen_helper_gvec_vmh8, },
{ .fno = gen_helper_gvec_vmh16, },
switch (s->fields->op2) {
case 0xa2:
- gen_gvec_fn_3(mul, es, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3));
+ gen_gvec_fn_3(mul, es, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
return DISAS_NEXT;
case 0xa3:
fn = &g_vmh[es];
g_assert_not_reached();
}
- gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), fn);
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), fn);
return DISAS_NEXT;
}
static DisasJumpType op_vnn(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_3(nand, ES_8, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3));
+ gen_gvec_fn_3(nand, ES_8, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vno(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_3(nor, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_3(nor, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vnx(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_3(eqv, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_3(eqv, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vo(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_3(or, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_3(or, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_voc(DisasContext *s, DisasOps *o)
{
- gen_gvec_fn_3(orc, ES_8, get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_3(orc, ES_8, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vpopct(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m3);
+ const uint8_t es = get_field(s, m3);
static const GVecGen2 g[4] = {
{ .fno = gen_helper_gvec_vpopct8, },
{ .fno = gen_helper_gvec_vpopct16, },
return DISAS_NORETURN;
}
- gen_gvec_2(get_field(s->fields, v1), get_field(s->fields, v2), &g[es]);
+ gen_gvec_2(get_field(s, v1), get_field(s, v2), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_verllv(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
static const GVecGen3 g[4] = {
{ .fno = gen_helper_gvec_verllv8, },
{ .fno = gen_helper_gvec_verllv16, },
return DISAS_NORETURN;
}
- gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), &g[es]);
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_verll(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
static const GVecGen2s g[4] = {
{ .fno = gen_helper_gvec_verll8, },
{ .fno = gen_helper_gvec_verll16, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec_2s(get_field(s->fields, v1), get_field(s->fields, v3), o->addr1,
+ gen_gvec_2s(get_field(s, v1), get_field(s, v3), o->addr1,
&g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_verim(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m5);
- const uint8_t i4 = get_field(s->fields, i4) &
+ const uint8_t es = get_field(s, m5);
+ const uint8_t i4 = get_field(s, i4) &
(NUM_VEC_ELEMENT_BITS(es) - 1);
static const GVecGen3i g[4] = {
{ .fno = gen_helper_gvec_verim8, },
return DISAS_NORETURN;
}
- gen_gvec_3i(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), i4, &g[es]);
+ gen_gvec_3i(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), i4, &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_vesv(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
- const uint8_t v1 = get_field(s->fields, v1);
- const uint8_t v2 = get_field(s->fields, v2);
- const uint8_t v3 = get_field(s->fields, v3);
+ const uint8_t es = get_field(s, m4);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t v3 = get_field(s, v3);
if (es > ES_64) {
gen_program_exception(s, PGM_SPECIFICATION);
static DisasJumpType op_ves(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
- const uint8_t d2 = get_field(s->fields, d2) &
+ const uint8_t es = get_field(s, m4);
+ const uint8_t d2 = get_field(s, d2) &
(NUM_VEC_ELEMENT_BITS(es) - 1);
- const uint8_t v1 = get_field(s->fields, v1);
- const uint8_t v3 = get_field(s->fields, v3);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v3 = get_field(s, v3);
TCGv_i32 shift;
if (es > ES_64) {
return DISAS_NORETURN;
}
- if (likely(!get_field(s->fields, b2))) {
+ if (likely(!get_field(s, b2))) {
switch (s->fields->op2) {
case 0x30:
gen_gvec_fn_2i(shli, es, v1, v3, d2);
{
TCGv_i64 shift = tcg_temp_new_i64();
- read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
if (s->fields->op2 == 0x74) {
tcg_gen_andi_i64(shift, shift, 0x7);
} else {
tcg_gen_andi_i64(shift, shift, 0x78);
}
- gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
shift, 0, gen_helper_gvec_vsl);
tcg_temp_free_i64(shift);
return DISAS_NEXT;
static DisasJumpType op_vsldb(DisasContext *s, DisasOps *o)
{
- const uint8_t i4 = get_field(s->fields, i4) & 0xf;
+ const uint8_t i4 = get_field(s, i4) & 0xf;
const int left_shift = (i4 & 7) * 8;
const int right_shift = 64 - left_shift;
TCGv_i64 t0 = tcg_temp_new_i64();
TCGv_i64 t2 = tcg_temp_new_i64();
if ((i4 & 8) == 0) {
- read_vec_element_i64(t0, get_field(s->fields, v2), 0, ES_64);
- read_vec_element_i64(t1, get_field(s->fields, v2), 1, ES_64);
- read_vec_element_i64(t2, get_field(s->fields, v3), 0, ES_64);
+ read_vec_element_i64(t0, get_field(s, v2), 0, ES_64);
+ read_vec_element_i64(t1, get_field(s, v2), 1, ES_64);
+ read_vec_element_i64(t2, get_field(s, v3), 0, ES_64);
} else {
- read_vec_element_i64(t0, get_field(s->fields, v2), 1, ES_64);
- read_vec_element_i64(t1, get_field(s->fields, v3), 0, ES_64);
- read_vec_element_i64(t2, get_field(s->fields, v3), 1, ES_64);
+ read_vec_element_i64(t0, get_field(s, v2), 1, ES_64);
+ read_vec_element_i64(t1, get_field(s, v3), 0, ES_64);
+ read_vec_element_i64(t2, get_field(s, v3), 1, ES_64);
}
tcg_gen_extract2_i64(t0, t1, t0, right_shift);
tcg_gen_extract2_i64(t1, t2, t1, right_shift);
- write_vec_element_i64(t0, get_field(s->fields, v1), 0, ES_64);
- write_vec_element_i64(t1, get_field(s->fields, v1), 1, ES_64);
+ write_vec_element_i64(t0, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(t1, get_field(s, v1), 1, ES_64);
tcg_temp_free(t0);
tcg_temp_free(t1);
{
TCGv_i64 shift = tcg_temp_new_i64();
- read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
if (s->fields->op2 == 0x7e) {
tcg_gen_andi_i64(shift, shift, 0x7);
} else {
tcg_gen_andi_i64(shift, shift, 0x78);
}
- gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
shift, 0, gen_helper_gvec_vsra);
tcg_temp_free_i64(shift);
return DISAS_NEXT;
{
TCGv_i64 shift = tcg_temp_new_i64();
- read_vec_element_i64(shift, get_field(s->fields, v3), 7, ES_8);
+ read_vec_element_i64(shift, get_field(s, v3), 7, ES_8);
if (s->fields->op2 == 0x7c) {
tcg_gen_andi_i64(shift, shift, 0x7);
} else {
tcg_gen_andi_i64(shift, shift, 0x78);
}
- gen_gvec_2i_ool(get_field(s->fields, v1), get_field(s->fields, v2),
+ gen_gvec_2i_ool(get_field(s, v1), get_field(s, v2),
shift, 0, gen_helper_gvec_vsrl);
tcg_temp_free_i64(shift);
return DISAS_NEXT;
static DisasJumpType op_vs(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
if (es > ES_128) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
} else if (es == ES_128) {
- gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3));
+ gen_gvec128_3_i64(tcg_gen_sub2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
return DISAS_NEXT;
}
- gen_gvec_fn_3(sub, es, get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3));
+ gen_gvec_fn_3(sub, es, get_field(s, v1), get_field(s, v2),
+ get_field(s, v3));
return DISAS_NEXT;
}
static DisasJumpType op_vscbi(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
static const GVecGen3 g[4] = {
{ .fno = gen_helper_gvec_vscbi8, },
{ .fno = gen_helper_gvec_vscbi16, },
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
} else if (es == ES_128) {
- gen_gvec128_3_i64(gen_scbi2_i64, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3));
+ gen_gvec128_3_i64(gen_scbi2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3));
return DISAS_NEXT;
}
- gen_gvec_3(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), &g[es]);
+ gen_gvec_3(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), &g[es]);
return DISAS_NEXT;
}
static DisasJumpType op_vsbi(DisasContext *s, DisasOps *o)
{
- if (get_field(s->fields, m5) != ES_128) {
+ if (get_field(s, m5) != ES_128) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec128_4_i64(gen_sbi2_i64, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3),
- get_field(s->fields, v4));
+ gen_gvec128_4_i64(gen_sbi2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3),
+ get_field(s, v4));
return DISAS_NEXT;
}
static DisasJumpType op_vsbcbi(DisasContext *s, DisasOps *o)
{
- if (get_field(s->fields, m5) != ES_128) {
+ if (get_field(s, m5) != ES_128) {
gen_program_exception(s, PGM_SPECIFICATION);
return DISAS_NORETURN;
}
- gen_gvec128_4_i64(gen_sbcbi2_i64, get_field(s->fields, v1),
- get_field(s->fields, v2), get_field(s->fields, v3),
- get_field(s->fields, v4));
+ gen_gvec128_4_i64(gen_sbcbi2_i64, get_field(s, v1),
+ get_field(s, v2), get_field(s, v3),
+ get_field(s, v4));
return DISAS_NEXT;
}
static DisasJumpType op_vsumg(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
TCGv_i64 sum, tmp;
uint8_t dst_idx;
uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 2;
const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 2 - 1;
- read_vec_element_i64(sum, get_field(s->fields, v3), max_idx, es);
+ read_vec_element_i64(sum, get_field(s, v3), max_idx, es);
for (; idx <= max_idx; idx++) {
- read_vec_element_i64(tmp, get_field(s->fields, v2), idx, es);
+ read_vec_element_i64(tmp, get_field(s, v2), idx, es);
tcg_gen_add_i64(sum, sum, tmp);
}
- write_vec_element_i64(sum, get_field(s->fields, v1), dst_idx, ES_64);
+ write_vec_element_i64(sum, get_field(s, v1), dst_idx, ES_64);
}
tcg_temp_free_i64(sum);
tcg_temp_free_i64(tmp);
static DisasJumpType op_vsumq(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
const uint8_t max_idx = NUM_VEC_ELEMENTS(es) - 1;
TCGv_i64 sumh, suml, zero, tmpl;
uint8_t idx;
zero = tcg_const_i64(0);
tmpl = tcg_temp_new_i64();
- read_vec_element_i64(suml, get_field(s->fields, v3), max_idx, es);
+ read_vec_element_i64(suml, get_field(s, v3), max_idx, es);
for (idx = 0; idx <= max_idx; idx++) {
- read_vec_element_i64(tmpl, get_field(s->fields, v2), idx, es);
+ read_vec_element_i64(tmpl, get_field(s, v2), idx, es);
tcg_gen_add2_i64(suml, sumh, suml, sumh, tmpl, zero);
}
- write_vec_element_i64(sumh, get_field(s->fields, v1), 0, ES_64);
- write_vec_element_i64(suml, get_field(s->fields, v1), 1, ES_64);
+ write_vec_element_i64(sumh, get_field(s, v1), 0, ES_64);
+ write_vec_element_i64(suml, get_field(s, v1), 1, ES_64);
tcg_temp_free_i64(sumh);
tcg_temp_free_i64(suml);
static DisasJumpType op_vsum(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
+ const uint8_t es = get_field(s, m4);
TCGv_i32 sum, tmp;
uint8_t dst_idx;
uint8_t idx = dst_idx * NUM_VEC_ELEMENTS(es) / 4;
const uint8_t max_idx = idx + NUM_VEC_ELEMENTS(es) / 4 - 1;
- read_vec_element_i32(sum, get_field(s->fields, v3), max_idx, es);
+ read_vec_element_i32(sum, get_field(s, v3), max_idx, es);
for (; idx <= max_idx; idx++) {
- read_vec_element_i32(tmp, get_field(s->fields, v2), idx, es);
+ read_vec_element_i32(tmp, get_field(s, v2), idx, es);
tcg_gen_add_i32(sum, sum, tmp);
}
- write_vec_element_i32(sum, get_field(s->fields, v1), dst_idx, ES_32);
+ write_vec_element_i32(sum, get_field(s, v1), dst_idx, ES_32);
}
tcg_temp_free_i32(sum);
tcg_temp_free_i32(tmp);
static DisasJumpType op_vtm(DisasContext *s, DisasOps *o)
{
- gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
cpu_env, 0, gen_helper_gvec_vtm);
set_cc_static(s);
return DISAS_NEXT;
static DisasJumpType op_vfae(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
- const uint8_t m5 = get_field(s->fields, m5);
+ const uint8_t es = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
static gen_helper_gvec_3 * const g[3] = {
gen_helper_gvec_vfae8,
gen_helper_gvec_vfae16,
}
if (extract32(m5, 0, 1)) {
- gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), cpu_env, m5, g_cc[es]);
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, m5, g_cc[es]);
set_cc_static(s);
} else {
- gen_gvec_3_ool(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), m5, g[es]);
+ gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), m5, g[es]);
}
return DISAS_NEXT;
}
static DisasJumpType op_vfee(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
- const uint8_t m5 = get_field(s->fields, m5);
+ const uint8_t es = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
static gen_helper_gvec_3 * const g[3] = {
gen_helper_gvec_vfee8,
gen_helper_gvec_vfee16,
}
if (extract32(m5, 0, 1)) {
- gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), cpu_env, m5, g_cc[es]);
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, m5, g_cc[es]);
set_cc_static(s);
} else {
- gen_gvec_3_ool(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), m5, g[es]);
+ gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), m5, g[es]);
}
return DISAS_NEXT;
}
static DisasJumpType op_vfene(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
- const uint8_t m5 = get_field(s->fields, m5);
+ const uint8_t es = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
static gen_helper_gvec_3 * const g[3] = {
gen_helper_gvec_vfene8,
gen_helper_gvec_vfene16,
}
if (extract32(m5, 0, 1)) {
- gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), cpu_env, m5, g_cc[es]);
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, m5, g_cc[es]);
set_cc_static(s);
} else {
- gen_gvec_3_ool(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), m5, g[es]);
+ gen_gvec_3_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), m5, g[es]);
}
return DISAS_NEXT;
}
static DisasJumpType op_vistr(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m4);
- const uint8_t m5 = get_field(s->fields, m5);
+ const uint8_t es = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
static gen_helper_gvec_2 * const g[3] = {
gen_helper_gvec_vistr8,
gen_helper_gvec_vistr16,
}
if (extract32(m5, 0, 1)) {
- gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
cpu_env, 0, g_cc[es]);
set_cc_static(s);
} else {
- gen_gvec_2_ool(get_field(s->fields, v1), get_field(s->fields, v2), 0,
+ gen_gvec_2_ool(get_field(s, v1), get_field(s, v2), 0,
g[es]);
}
return DISAS_NEXT;
static DisasJumpType op_vstrc(DisasContext *s, DisasOps *o)
{
- const uint8_t es = get_field(s->fields, m5);
- const uint8_t m6 = get_field(s->fields, m6);
+ const uint8_t es = get_field(s, m5);
+ const uint8_t m6 = get_field(s, m6);
static gen_helper_gvec_4 * const g[3] = {
gen_helper_gvec_vstrc8,
gen_helper_gvec_vstrc16,
if (extract32(m6, 0, 1)) {
if (extract32(m6, 2, 1)) {
- gen_gvec_4_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), get_field(s->fields, v4),
+ gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
cpu_env, m6, g_cc_rt[es]);
} else {
- gen_gvec_4_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), get_field(s->fields, v4),
+ gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
cpu_env, m6, g_cc[es]);
}
set_cc_static(s);
} else {
if (extract32(m6, 2, 1)) {
- gen_gvec_4_ool(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), get_field(s->fields, v4),
+ gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
m6, g_rt[es]);
} else {
- gen_gvec_4_ool(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), get_field(s->fields, v4),
+ gen_gvec_4_ool(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4),
m6, g[es]);
}
}
static DisasJumpType op_vfa(DisasContext *s, DisasOps *o)
{
- const uint8_t fpf = get_field(s->fields, m4);
- const uint8_t m5 = get_field(s->fields, m5);
+ const uint8_t fpf = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
const bool se = extract32(m5, 3, 1);
gen_helper_gvec_3_ptr *fn;
default:
g_assert_not_reached();
}
- gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), cpu_env, 0, fn);
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, 0, fn);
return DISAS_NEXT;
}
static DisasJumpType op_wfc(DisasContext *s, DisasOps *o)
{
- const uint8_t fpf = get_field(s->fields, m3);
- const uint8_t m4 = get_field(s->fields, m4);
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
if (fpf != FPF_LONG || m4) {
gen_program_exception(s, PGM_SPECIFICATION);
}
if (s->fields->op2 == 0xcb) {
- gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
cpu_env, 0, gen_helper_gvec_wfc64);
} else {
- gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2),
cpu_env, 0, gen_helper_gvec_wfk64);
}
set_cc_static(s);
static DisasJumpType op_vfc(DisasContext *s, DisasOps *o)
{
- const uint8_t fpf = get_field(s->fields, m4);
- const uint8_t m5 = get_field(s->fields, m5);
- const uint8_t m6 = get_field(s->fields, m6);
+ const uint8_t fpf = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
+ const uint8_t m6 = get_field(s, m6);
const bool se = extract32(m5, 3, 1);
const bool cs = extract32(m6, 0, 1);
gen_helper_gvec_3_ptr *fn;
g_assert_not_reached();
}
}
- gen_gvec_3_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), cpu_env, 0, fn);
+ gen_gvec_3_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), cpu_env, 0, fn);
if (cs) {
set_cc_static(s);
}
static DisasJumpType op_vcdg(DisasContext *s, DisasOps *o)
{
- const uint8_t fpf = get_field(s->fields, m3);
- const uint8_t m4 = get_field(s->fields, m4);
- const uint8_t erm = get_field(s->fields, m5);
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
+ const uint8_t erm = get_field(s, m5);
const bool se = extract32(m4, 3, 1);
gen_helper_gvec_2_ptr *fn;
default:
g_assert_not_reached();
}
- gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
deposit32(m4, 4, 4, erm), fn);
return DISAS_NEXT;
}
static DisasJumpType op_vfll(DisasContext *s, DisasOps *o)
{
- const uint8_t fpf = get_field(s->fields, m3);
- const uint8_t m4 = get_field(s->fields, m4);
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfll32;
if (fpf != FPF_SHORT || extract32(m4, 0, 3)) {
if (extract32(m4, 3, 1)) {
fn = gen_helper_gvec_vfll32s;
}
- gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
0, fn);
return DISAS_NEXT;
}
static DisasJumpType op_vfma(DisasContext *s, DisasOps *o)
{
- const uint8_t m5 = get_field(s->fields, m5);
- const uint8_t fpf = get_field(s->fields, m6);
+ const uint8_t m5 = get_field(s, m5);
+ const uint8_t fpf = get_field(s, m6);
const bool se = extract32(m5, 3, 1);
gen_helper_gvec_4_ptr *fn;
} else {
fn = se ? gen_helper_gvec_vfms64s : gen_helper_gvec_vfms64;
}
- gen_gvec_4_ptr(get_field(s->fields, v1), get_field(s->fields, v2),
- get_field(s->fields, v3), get_field(s->fields, v4), cpu_env,
+ gen_gvec_4_ptr(get_field(s, v1), get_field(s, v2),
+ get_field(s, v3), get_field(s, v4), cpu_env,
0, fn);
return DISAS_NEXT;
}
static DisasJumpType op_vfpso(DisasContext *s, DisasOps *o)
{
- const uint8_t v1 = get_field(s->fields, v1);
- const uint8_t v2 = get_field(s->fields, v2);
- const uint8_t fpf = get_field(s->fields, m3);
- const uint8_t m4 = get_field(s->fields, m4);
- const uint8_t m5 = get_field(s->fields, m5);
+ const uint8_t v1 = get_field(s, v1);
+ const uint8_t v2 = get_field(s, v2);
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
TCGv_i64 tmp;
if (fpf != FPF_LONG || extract32(m4, 0, 3) || m5 > 2) {
static DisasJumpType op_vfsq(DisasContext *s, DisasOps *o)
{
- const uint8_t fpf = get_field(s->fields, m3);
- const uint8_t m4 = get_field(s->fields, m4);
+ const uint8_t fpf = get_field(s, m3);
+ const uint8_t m4 = get_field(s, m4);
gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vfsq64;
if (fpf != FPF_LONG || extract32(m4, 0, 3)) {
if (extract32(m4, 3, 1)) {
fn = gen_helper_gvec_vfsq64s;
}
- gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env,
0, fn);
return DISAS_NEXT;
}
static DisasJumpType op_vftci(DisasContext *s, DisasOps *o)
{
- const uint16_t i3 = get_field(s->fields, i3);
- const uint8_t fpf = get_field(s->fields, m4);
- const uint8_t m5 = get_field(s->fields, m5);
+ const uint16_t i3 = get_field(s, i3);
+ const uint8_t fpf = get_field(s, m4);
+ const uint8_t m5 = get_field(s, m5);
gen_helper_gvec_2_ptr *fn = gen_helper_gvec_vftci64;
if (fpf != FPF_LONG || extract32(m5, 0, 3)) {
if (extract32(m5, 3, 1)) {
fn = gen_helper_gvec_vftci64s;
}
- gen_gvec_2_ptr(get_field(s->fields, v1), get_field(s->fields, v2), cpu_env,
- i3, fn);
+ gen_gvec_2_ptr(get_field(s, v1), get_field(s, v2), cpu_env, i3, fn);
set_cc_static(s);
return DISAS_NEXT;
}
projects / qemu-nvme.git / commitdiff