]> www.infradead.org Git - users/dwmw2/linux.git/commitdiff
x86/bhi: Mitigate KVM by default
authorPawan Gupta <pawan.kumar.gupta@linux.intel.com>
Mon, 11 Mar 2024 15:57:09 +0000 (08:57 -0700)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Wed, 10 Apr 2024 14:19:44 +0000 (16:19 +0200)
commit 95a6ccbdc7199a14b71ad8901cb788ba7fb5167b upstream.

BHI mitigation mode spectre_bhi=auto does not deploy the software
mitigation by default. In a cloud environment, it is a likely scenario
where userspace is trusted but the guests are not trusted. Deploying
system wide mitigation in such cases is not desirable.

Update the auto mode to unconditionally mitigate against malicious
guests. Deploy the software sequence at VMexit in auto mode also, when
hardware mitigation is not available. Unlike the force =on mode,
software sequence is not deployed at syscalls in auto mode.

Suggested-by: Alexandre Chartre <alexandre.chartre@oracle.com>
Signed-off-by: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Alexandre Chartre <alexandre.chartre@oracle.com>
Reviewed-by: Josh Poimboeuf <jpoimboe@kernel.org>
Signed-off-by: Daniel Sneddon <daniel.sneddon@linux.intel.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Documentation/admin-guide/hw-vuln/spectre.rst
Documentation/admin-guide/kernel-parameters.txt
arch/x86/include/asm/cpufeatures.h
arch/x86/include/asm/nospec-branch.h
arch/x86/kernel/cpu/bugs.c
arch/x86/kvm/vmx/vmenter.S

index 48e0ce36ae67dd430949fe8512bddc48bfec854e..fda00aac0d721f7d63c169508be47f5f075f31bd 100644 (file)
@@ -439,10 +439,12 @@ The possible values in this file are:
    - System is protected by retpoline
  * - BHI: BHI_DIS_S
    - System is protected by BHI_DIS_S
- * - BHI: SW loop
+ * - BHI: SW loop; KVM SW loop
    - System is protected by software clearing sequence
  * - BHI: Syscall hardening
    - Syscalls are hardened against BHI
+ * - BHI: Syscall hardening; KVM: SW loop
+   - System is protected from userspace attacks by syscall hardening; KVM is protected by software clearing sequence
 
 Full mitigation might require a microcode update from the CPU
 vendor. When the necessary microcode is not available, the kernel will
@@ -719,7 +721,8 @@ For user space mitigation:
                        unconditionally disable.
                auto
                        enable if hardware mitigation
-                       control(BHI_DIS_S) is available.
+                       control(BHI_DIS_S) is available, otherwise
+                       enable alternate mitigation in KVM.
 
 For spectre_v2_user see Documentation/admin-guide/kernel-parameters.txt
 
index 6576545921dc4ac13dd0ff1aef42ca962cc1ea50..7e9e655a715eabbe4f9fa1038f3ce3f3e02a1eca 100644 (file)
 
                        on   - unconditionally enable.
                        off  - unconditionally disable.
-                       auto - (default) enable only if hardware mitigation
-                              control(BHI_DIS_S) is available.
+                       auto - (default) enable hardware mitigation
+                              (BHI_DIS_S) if available, otherwise enable
+                              alternate mitigation in KVM.
 
        spectre_v2=     [X86] Control mitigation of Spectre variant 2
                        (indirect branch speculation) vulnerability.
index 08d196a0bb00d1bcd2e54cc023c8ed43648e762d..18817817ea81bf189356ecffa261dddacdb7f97c 100644 (file)
 #define X86_FEATURE_CLEAR_BHB_LOOP     (21*32+ 1) /* "" Clear branch history at syscall entry using SW loop */
 #define X86_FEATURE_BHI_CTRL           (21*32+ 2) /* "" BHI_DIS_S HW control available */
 #define X86_FEATURE_CLEAR_BHB_HW       (21*32+ 3) /* "" BHI_DIS_S HW control enabled */
+#define X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT (21*32+ 4) /* "" Clear branch history at vmexit using SW loop */
 
 /*
  * BUG word(s)
index 057b88c647e336b6d3368abfb64257222420e757..ed582fa98cb2c7b12f314cfe2f9fe0993b8b1f20 100644 (file)
 .macro CLEAR_BRANCH_HISTORY
        ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP
 .endm
+
+.macro CLEAR_BRANCH_HISTORY_VMEXIT
+       ALTERNATIVE "", "call clear_bhb_loop", X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT
+.endm
 #else
 #define CLEAR_BRANCH_HISTORY
+#define CLEAR_BRANCH_HISTORY_VMEXIT
 #endif
 
 #else /* __ASSEMBLY__ */
index 555a8928f5886a317db64397f2dd0449dea0b17c..50fdd6ca3b787ddb53c9378f48bc0d15dfd23409 100644 (file)
@@ -1645,9 +1645,14 @@ static void __init bhi_select_mitigation(void)
        if (!IS_ENABLED(CONFIG_X86_64))
                return;
 
+       /* Mitigate KVM by default */
+       setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT);
+       pr_info("Spectre BHI mitigation: SW BHB clearing on vm exit\n");
+
        if (bhi_mitigation == BHI_MITIGATION_AUTO)
                return;
 
+       /* Mitigate syscalls when the mitigation is forced =on */
        setup_force_cpu_cap(X86_FEATURE_CLEAR_BHB_LOOP);
        pr_info("Spectre BHI mitigation: SW BHB clearing on syscall\n");
 }
@@ -2790,10 +2795,12 @@ static const char * const spectre_bhi_state(void)
        else if  (boot_cpu_has(X86_FEATURE_CLEAR_BHB_HW))
                return "; BHI: BHI_DIS_S";
        else if  (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP))
-               return "; BHI: SW loop";
+               return "; BHI: SW loop, KVM: SW loop";
        else if (boot_cpu_has(X86_FEATURE_RETPOLINE) &&
                 !(x86_read_arch_cap_msr() & ARCH_CAP_RRSBA))
                return "; BHI: Retpoline";
+       else if  (boot_cpu_has(X86_FEATURE_CLEAR_BHB_LOOP_ON_VMEXIT))
+               return "; BHI: Syscall hardening, KVM: SW loop";
 
        return "; BHI: Vulnerable (Syscall hardening enabled)";
 }
index 3b5d0e35bdb244e60b241a9342e82efbcd8dbcfa..ef61bd6d071facff545db3434c2e52c01527ac88 100644 (file)
@@ -213,7 +213,7 @@ SYM_INNER_LABEL(vmx_vmexit, SYM_L_GLOBAL)
 
        call vmx_spec_ctrl_restore_host
 
-       CLEAR_BRANCH_HISTORY
+       CLEAR_BRANCH_HISTORY_VMEXIT
 
        /* Put return value in AX */
        mov %_ASM_BX, %_ASM_AX