arm64: dts: exynos990: Add CMU_PERIS and MCT nodes

CMU_PERIS is a new clock controller that clocks the MCT. The MCT has 9
timers (1x count-up global timer, 8x count-down CPU local).
The global timer generates 4 interrupts, and each local timer
generates one interrupt. So, in total 12 interrupts.

Signed-off-by: Igor Belwon <igor.belwon@mentallysanemainliners.org>
Link: https://lore.kernel.org/r/20250104-cmu-nodes-v1-2-ae8af253bc25@mentallysanemainliners.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

diff --git a/arch/arm64/boot/dts/exynos/exynos990.dtsi b/arch/arm64/boot/dts/exynos/exynos990.dtsi
index 9d017dbed9523e874891f13258d331c3e829ca03..0e18711cbdc98a65cbd2d709cdd53a7680b833f2 100644 (file)
--- a/arch/arm64/boot/dts/exynos/exynos990.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos990.dtsi
@@ -181,6 +181,36 @@
                        reg = <0x10000000 0x100>;
                };
 
+               cmu_peris: clock-controller@10020000 {
+                       compatible = "samsung,exynos990-cmu-peris";
+                       reg = <0x10020000 0x8000>;
+                       #clock-cells = <1>;
+
+                       clocks = <&oscclk>,
+                                <&cmu_top CLK_DOUT_CMU_PERIS_BUS>;
+                       clock-names = "oscclk", "bus";
+               };
+
+               timer@10040000 {
+                       compatible = "samsung,exynos990-mct",
+                                    "samsung,exynos4210-mct";
+                       reg = <0x10040000 0x800>;
+                       clocks = <&oscclk>, <&cmu_peris CLK_GOUT_PERIS_MCT_PCLK>;
+                       clock-names = "fin_pll", "mct";
+                       interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 469 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 470 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 471 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 472 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 473 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 475 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+                                    <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
+               };
+
                gic: interrupt-controller@10101000 {
                        compatible = "arm,gic-400";
                        reg = <0x10101000 0x1000>,