drm/amd/display: 3DLUT non-DMA refactor

[Why]
Currently the handling for 3DLUT is found in multiple different
places, which causes issues when the different functions are not
in sync with each other.
Frequently bugs occur because the LUT handling is broken up, and
what has already been handled isn't kept track of well, which can
cause earlier changes to the LUT params to be overridden.

[How]
Remove DMA LUT handling from DCN401 and refactor legacy LUT
handling in one place to make it easier to keep track of what has
and needs to be done.

Reviewed-by: Ilya Bakoulin <ilya.bakoulin@amd.com>
Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com>
Signed-off-by: Tom Chung <chiahsuan.chung@amd.com>
Tested-by: Daniel Wheeler <daniel.wheeler@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
index 968b010971ea8c7a6afa37e3c6478d06d62af946..58bed01fc20e6319526d8ed5da1bdb82cf697534 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn32/dcn32_init.c
@@ -162,7 +162,6 @@ static const struct hwseq_private_funcs dcn32_private_funcs = {
        .is_dp_dig_pixel_rate_div_policy = dcn32_is_dp_dig_pixel_rate_div_policy,
        .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,
        .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe,
-       .populate_mcm_luts = dcn401_populate_mcm_luts,
 };
 
 void dcn32_hw_sequencer_init_functions(struct dc *dc)

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
index 77489bbcda02a73f80f9644b338e8f232bb4d6e3..44c1184868e095476d44a8ed6c4e0f63d144fdcc 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_hwseq.c
@@ -670,46 +670,40 @@ bool dcn401_set_mcm_luts(struct pipe_ctx *pipe_ctx,
        struct dpp *dpp_base = pipe_ctx->plane_res.dpp;
        int mpcc_id = pipe_ctx->plane_res.hubp->inst;
        struct mpc *mpc = pipe_ctx->stream_res.opp->ctx->dc->res_pool->mpc;
-       bool result = true;
+       bool result;
        const struct pwl_params *lut_params = NULL;
        bool rval;
 
        mpc->funcs->set_movable_cm_location(mpc, MPCC_MOVABLE_CM_LOCATION_BEFORE, mpcc_id);
        pipe_ctx->plane_state->mcm_location = MPCC_MOVABLE_CM_LOCATION_BEFORE;
        // 1D LUT
-       if (plane_state->mcm_shaper_3dlut_setting == DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL) {
-               if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
-                       lut_params = &plane_state->blend_tf.pwl;
-               else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
-                       rval = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf,
-                                       &dpp_base->regamma_params, false);
-                       lut_params = rval ? &dpp_base->regamma_params : NULL;
-               }
-               result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
-               lut_params = NULL;
+       if (plane_state->blend_tf.type == TF_TYPE_HWPWL)
+               lut_params = &plane_state->blend_tf.pwl;
+       else if (plane_state->blend_tf.type == TF_TYPE_DISTRIBUTED_POINTS) {
+               rval = cm3_helper_translate_curve_to_hw_format(&plane_state->blend_tf,
+                               &dpp_base->regamma_params, false);
+               lut_params = rval ? &dpp_base->regamma_params : NULL;
        }
+       result = mpc->funcs->program_1dlut(mpc, lut_params, mpcc_id);
+       lut_params = NULL;
 
        // Shaper
-       if (plane_state->mcm_shaper_3dlut_setting == DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL) {
-               if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)
-                       lut_params = &plane_state->in_shaper_func.pwl;
-               else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {
-                       // TODO: dpp_base replace
-                       ASSERT(false);
-                       rval = cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func,
-                                       &dpp_base->shaper_params, true);
-                       lut_params = rval ? &dpp_base->shaper_params : NULL;
-               }
-
-               result = mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
+       if (plane_state->in_shaper_func.type == TF_TYPE_HWPWL)
+               lut_params = &plane_state->in_shaper_func.pwl;
+       else if (plane_state->in_shaper_func.type == TF_TYPE_DISTRIBUTED_POINTS) {
+               // TODO: dpp_base replace
+               rval = cm3_helper_translate_curve_to_hw_format(&plane_state->in_shaper_func,
+                               &dpp_base->shaper_params, true);
+               lut_params = rval ? &dpp_base->shaper_params : NULL;
        }
+       result &= mpc->funcs->program_shaper(mpc, lut_params, mpcc_id);
 
        // 3D
-       if (plane_state->mcm_shaper_3dlut_setting == DC_CM2_SHAPER_3DLUT_SETTING_BYPASS_ALL) {
+       if (mpc->funcs->program_3dlut) {
                if (plane_state->lut3d_func.state.bits.initialized == 1)
-                       result = mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);
+                       result &= mpc->funcs->program_3dlut(mpc, &plane_state->lut3d_func.lut_3d, mpcc_id);
                else
-                       result = mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
+                       result &= mpc->funcs->program_3dlut(mpc, NULL, mpcc_id);
        }
 
        return result;

diff --git a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
index 457f4167e84825c1cb1cdec8689319e10864642a..f4eda4a55ea72f9eca055bd63d8f3a008e8eb98e 100644 (file)
--- a/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
+++ b/drivers/gpu/drm/amd/display/dc/hwss/dcn401/dcn401_init.c
@@ -136,7 +136,7 @@ static const struct hwseq_private_funcs dcn401_private_funcs = {
        .calculate_dccg_k1_k2_values = NULL,
        .apply_single_controller_ctx_to_hw = dce110_apply_single_controller_ctx_to_hw,
        .reset_back_end_for_pipe = dcn20_reset_back_end_for_pipe,
-       .populate_mcm_luts = dcn401_populate_mcm_luts,
+       .populate_mcm_luts = NULL,
 };
 
 void dcn401_hw_sequencer_init_functions(struct dc *dc)