case FBC_MULTIPLE_PIPES:
                        seq_printf(m, "multiple pipes are enabled");
                        break;
+               case FBC_MODULE_PARAM:
+                       seq_printf(m, "disabled per module param (default off)");
+                       break;
                default:
                        seq_printf(m, "unknown reason");
                }
 
 unsigned int i915_enable_rc6 = 0;
 module_param_named(i915_enable_rc6, i915_enable_rc6, int, 0600);
 
+unsigned int i915_enable_fbc = 0;
+module_param_named(i915_enable_fbc, i915_enable_fbc, int, 0600);
+
 unsigned int i915_lvds_downclock = 0;
 module_param_named(lvds_downclock, i915_lvds_downclock, int, 0400);
 
 static const struct intel_device_info intel_ironlake_m_info = {
        .gen = 5, .is_mobile = 1,
        .need_gfx_hws = 1, .has_hotplug = 1,
-       .has_fbc = 0, /* disabled due to buggy hardware */
+       .has_fbc = 1,
        .has_bsd_ring = 1,
 };
 
 
        FBC_BAD_PLANE, /* fbc not supported on plane */
        FBC_NOT_TILED, /* buffer not tiled */
        FBC_MULTIPLE_PIPES, /* more than one pipe active */
+       FBC_MODULE_PARAM,
 };
 
 enum intel_pch {
 extern unsigned int i915_panel_use_ssc;
 extern int i915_vbt_sdvo_panel_type;
 extern unsigned int i915_enable_rc6;
+extern unsigned int i915_enable_fbc;
 
 extern int i915_suspend(struct drm_device *dev, pm_message_t state);
 extern int i915_resume(struct drm_device *dev);
 
        intel_fb = to_intel_framebuffer(fb);
        obj = intel_fb->obj;
 
+       if (!i915_enable_fbc) {
+               DRM_DEBUG_KMS("fbc disabled per module param (default off)\n");
+               dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
+               goto out_disable;
+       }
        if (intel_fb->obj->base.size > dev_priv->cfb_size) {
                DRM_DEBUG_KMS("framebuffer too large, disabling "
                              "compression\n");