disabled |= (I915_SCHEDULER_CAP_ENABLED |
                                     I915_SCHEDULER_CAP_PRIORITY);
 
-               if (intel_uc_uses_guc_submission(&i915->gt.uc))
+               if (intel_uc_uses_guc_submission(&to_gt(i915)->uc))
                        enabled |= I915_SCHEDULER_CAP_STATIC_PRIORITY_MAP;
 
                for (i = 0; i < ARRAY_SIZE(map); i++) {
 
 {
        int ret;
 
-       ret = ggtt_probe_hw(&i915->ggtt, &i915->gt);
+       ret = ggtt_probe_hw(&i915->ggtt, to_gt(i915));
        if (ret)
                return ret;
 
 
                return 0;
 
        with_intel_runtime_pm(&i915->runtime_pm, wakeref) {
-               struct intel_ips *ips = &i915->gt.rps.ips;
+               struct intel_ips *ips = &to_gt(i915)->rps.ips;
 
                spin_lock_irq(&mchdev_lock);
                chipset_val = __ips_chipset_val(ips);
        if (!i915)
                return false;
 
-       rps = &i915->gt.rps;
+       rps = &to_gt(i915)->rps;
 
        spin_lock_irq(&mchdev_lock);
        if (rps->max_freq_softlimit < rps->max_freq)
        if (!i915)
                return false;
 
-       rps = &i915->gt.rps;
+       rps = &to_gt(i915)->rps;
 
        spin_lock_irq(&mchdev_lock);
        if (rps->max_freq_softlimit > rps->min_freq)
        if (!i915)
                return false;
 
-       ret = i915->gt.awake;
+       ret = to_gt(i915)->awake;
 
        drm_dev_put(&i915->drm);
        return ret;
        if (!i915)
                return false;
 
-       rps = &i915->gt.rps;
+       rps = &to_gt(i915)->rps;
 
        spin_lock_irq(&mchdev_lock);
        rps->max_freq_softlimit = rps->min_freq;
-       ret = !__gen5_rps_set(&i915->gt.rps, rps->min_freq);
+       ret = !__gen5_rps_set(&to_gt(i915)->rps, rps->min_freq);
        spin_unlock_irq(&mchdev_lock);
 
        drm_dev_put(&i915->drm);
 
 static void
 gen9_wa_init_mcr(struct drm_i915_private *i915, struct i915_wa_list *wal)
 {
-       const struct sseu_dev_info *sseu = &i915->gt.info.sseu;
+       const struct sseu_dev_info *sseu = &to_gt(i915)->info.sseu;
        unsigned int slice, subslice;
        u32 mcr, mcr_mask;
 
 
        struct mock_engine *engine;
 
        GEM_BUG_ON(id >= I915_NUM_ENGINES);
-       GEM_BUG_ON(!i915->gt.uncore);
+       GEM_BUG_ON(!to_gt(i915)->uncore);
 
        engine = kzalloc(sizeof(*engine) + PAGE_SIZE, GFP_KERNEL);
        if (!engine)
 
        /* minimal engine setup for requests */
        engine->base.i915 = i915;
-       engine->base.gt = &i915->gt;
-       engine->base.uncore = i915->gt.uncore;
+       engine->base.gt = to_gt(i915);
+       engine->base.uncore = to_gt(i915)->uncore;
        snprintf(engine->base.name, sizeof(engine->base.name), "%s", name);
        engine->base.id = id;
        engine->base.mask = BIT(id);
 
        engine->base.release = mock_engine_release;
 
-       i915->gt.engine[id] = &engine->base;
-       i915->gt.engine_class[0][id] = &engine->base;
+       to_gt(i915)->engine[id] = &engine->base;
+       to_gt(i915)->engine_class[0][id] = &engine->base;
 
        /* fake hw queue */
        spin_lock_init(&engine->hw_lock);
 
                SUBTEST(live_active_context),
                SUBTEST(live_remote_context),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (intel_gt_is_wedged(gt))
                return 0;
 
                live_engine_pm_selftests,
                NULL,
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
        typeof(*tests) *fn;
 
        for (fn = tests; *fn; fn++) {
 
                SUBTEST(perf_mi_noop),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
 static int intel_mmio_bases_check(void *arg)
 
        int saved_hangcheck;
        int err;
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
        saved_hangcheck = i915->params.enable_hangcheck;
        i915->params.enable_hangcheck = INT_MAX;
 
-       err = intel_gt_live_subtests(tests, &i915->gt);
+       err = intel_gt_live_subtests(tests, to_gt(i915));
 
        i915->params.enable_hangcheck = saved_hangcheck;
        return err;
 
                SUBTEST(live_virtual_reset),
        };
 
-       if (i915->gt.submission_method != INTEL_SUBMISSION_ELSP)
+       if (to_gt(i915)->submission_method != INTEL_SUBMISSION_ELSP)
                return 0;
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
                SUBTEST(live_gt_resume),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
 int intel_gt_pm_late_selftests(struct drm_i915_private *i915)
                SUBTEST(live_rc6_ctx_wa),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
                SUBTEST(igt_reset_evict_fence),
                SUBTEST(igt_handle_error),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
        intel_wakeref_t wakeref;
        int err;
 
 
        if (!HAS_LOGICAL_RING_CONTEXTS(i915))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
                SUBTEST(thread_global_copy),
                SUBTEST(thread_global_clear),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (!gt->migrate.context)
                return 0;
                SUBTEST(perf_clear_blt),
                SUBTEST(perf_copy_blt),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (intel_gt_is_wedged(gt))
                return 0;
 
        if (!get_mocs_settings(i915, &table))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
                SUBTEST(igt_atomic_reset),
                SUBTEST(igt_atomic_engine_reset),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (!intel_has_gpu_reset(gt))
                return 0;
 
                SUBTEST(live_ctx_switch_wa),
        };
 
-       if (i915->gt.submission_method > INTEL_SUBMISSION_RING)
+       if (to_gt(i915)->submission_method > INTEL_SUBMISSION_RING)
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
 static int live_slpc_clamp_min(void *arg)
 {
        struct drm_i915_private *i915 = arg;
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
        struct intel_guc_slpc *slpc = >->uc.guc.slpc;
        struct intel_rps *rps = >->rps;
        struct intel_engine_cs *engine;
 static int live_slpc_clamp_max(void *arg)
 {
        struct drm_i915_private *i915 = arg;
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
        struct intel_guc_slpc *slpc;
        struct intel_rps *rps;
        struct intel_engine_cs *engine;
                SUBTEST(live_slpc_clamp_min),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
        return i915_live_subtests(tests, i915);
 
        INIT_RADIX_TREE(&state.cachelines, GFP_KERNEL);
        state.prng = I915_RND_STATE_INITIALIZER(i915_selftest.random_seed);
 
-       state.gt = &i915->gt;
+       state.gt = to_gt(i915);
 
        /*
         * Create a bunch of timelines and check that their HWSP do not overlap.
                SUBTEST(live_hwsp_rollover_user),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
                SUBTEST(live_engine_reset_workarounds),
        };
 
-       if (intel_gt_is_wedged(&i915->gt))
+       if (intel_gt_is_wedged(to_gt(i915)))
                return 0;
 
-       return intel_gt_live_subtests(tests, &i915->gt);
+       return intel_gt_live_subtests(tests, to_gt(i915));
 }
 
        if (unlikely(ret < 0))
                return ret;
 
-       intel_guc_pm_intrmsk_enable(&i915->gt);
+       intel_guc_pm_intrmsk_enable(to_gt(i915));
 
        slpc_get_rp_values(slpc);
 
 
                SUBTEST(intel_guc_scrub_ctbs),
                SUBTEST(intel_guc_steal_guc_ids),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (intel_gt_is_wedged(gt))
                return 0;
 
        static const struct i915_subtest tests[] = {
                SUBTEST(intel_guc_multi_lrc_basic),
        };
-       struct intel_gt *gt = &i915->gt;
+       struct intel_gt *gt = to_gt(i915);
 
        if (intel_gt_is_wedged(gt))
                return 0;