riscv, bpf: Optimize zextw insn with Zba extension

The Zba extension provides add.uw insn which can be used to implement
zext.w with rs2 set as ZERO.

Signed-off-by: Xiao Wang <xiao.w.wang@intel.com>
Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
Tested-by: Pu Lehui <pulehui@huawei.com>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Reviewed-by: Pu Lehui <pulehui@huawei.com>
Link: https://lore.kernel.org/bpf/20240516090430.493122-1-xiao.w.wang@intel.com

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 9e87287942dca1101efb2988a1a43e7912208ab7..6b8f1059594d84838c7070c6d945ddcb56a60374 100644 (file)
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -595,6 +595,18 @@ config TOOLCHAIN_HAS_VECTOR_CRYPTO
        def_bool $(as-instr, .option arch$(comma) +v$(comma) +zvkb)
        depends on AS_HAS_OPTION_ARCH
 
+config RISCV_ISA_ZBA
+       bool "Zba extension support for bit manipulation instructions"
+       default y
+       help
+          Add support for enabling optimisations in the kernel when the Zba
+          extension is detected at boot.
+
+          The Zba extension provides instructions to accelerate the generation
+          of addresses that index into arrays of basic data types.
+
+          If you don't know what to do here, say Y.
+
 config RISCV_ISA_ZBB
        bool "Zbb extension support for bit manipulation instructions"
        depends on TOOLCHAIN_HAS_ZBB

diff --git a/arch/riscv/net/bpf_jit.h b/arch/riscv/net/bpf_jit.h
index fdbf88ca8b700d021b21df2985651bf58fec8574..97041b58237a83d89f8cc90b95a9894efdd9f059 100644 (file)
--- a/arch/riscv/net/bpf_jit.h
+++ b/arch/riscv/net/bpf_jit.h
@@ -18,6 +18,11 @@ static inline bool rvc_enabled(void)
        return IS_ENABLED(CONFIG_RISCV_ISA_C);
 }
 
+static inline bool rvzba_enabled(void)
+{
+       return IS_ENABLED(CONFIG_RISCV_ISA_ZBA) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBA);
+}
+
 static inline bool rvzbb_enabled(void)
 {
        return IS_ENABLED(CONFIG_RISCV_ISA_ZBB) && riscv_has_extension_likely(RISCV_ISA_EXT_ZBB);
@@ -939,6 +944,14 @@ static inline u16 rvc_sdsp(u32 imm9, u8 rs2)
        return rv_css_insn(0x7, imm, rs2, 0x2);
 }
 
+/* RV64-only ZBA instructions. */
+
+static inline u32 rvzba_zextw(u8 rd, u8 rs1)
+{
+       /* add.uw rd, rs1, ZERO */
+       return rv_r_insn(0x04, RV_REG_ZERO, rs1, 0, rd, 0x3b);
+}
+
 #endif /* __riscv_xlen == 64 */
 
 /* Helper functions that emit RVC instructions when possible. */
@@ -1161,6 +1174,11 @@ static inline void emit_zexth(u8 rd, u8 rs, struct rv_jit_context *ctx)
 
 static inline void emit_zextw(u8 rd, u8 rs, struct rv_jit_context *ctx)
 {
+       if (rvzba_enabled()) {
+               emit(rvzba_zextw(rd, rs), ctx);
+               return;
+       }
+
        emit_slli(rd, rs, 32, ctx);
        emit_srli(rd, rd, 32, ctx);
 }