unsigned long gma_head, gma_tail, gma_bottom, ring_size, ring_tail;
        struct parser_exec_state s;
        int ret = 0;
+       struct intel_vgpu_workload *workload = container_of(wa_ctx,
+                               struct intel_vgpu_workload,
+                               wa_ctx);
 
        /* ring base is page aligned */
        if (WARN_ON(!IS_ALIGNED(wa_ctx->indirect_ctx.guest_gma, GTT_PAGE_SIZE)))
 
        s.buf_type = RING_BUFFER_INSTRUCTION;
        s.buf_addr_type = GTT_BUFFER;
-       s.vgpu = wa_ctx->workload->vgpu;
-       s.ring_id = wa_ctx->workload->ring_id;
+       s.vgpu = workload->vgpu;
+       s.ring_id = workload->ring_id;
        s.ring_start = wa_ctx->indirect_ctx.guest_gma;
        s.ring_size = ring_size;
        s.ring_head = gma_head;
        s.ring_tail = gma_tail;
        s.rb_va = wa_ctx->indirect_ctx.shadow_va;
-       s.workload = wa_ctx->workload;
+       s.workload = workload;
 
        ret = ip_gma_set(&s, gma_head);
        if (ret)
 {
        int ctx_size = wa_ctx->indirect_ctx.size;
        unsigned long guest_gma = wa_ctx->indirect_ctx.guest_gma;
-       struct intel_vgpu *vgpu = wa_ctx->workload->vgpu;
+       struct intel_vgpu_workload *workload = container_of(wa_ctx,
+                                       struct intel_vgpu_workload,
+                                       wa_ctx);
+       struct intel_vgpu *vgpu = workload->vgpu;
        struct drm_i915_gem_object *obj;
        int ret = 0;
        void *map;
 
-       obj = i915_gem_object_create(wa_ctx->workload->vgpu->gvt->dev_priv,
+       obj = i915_gem_object_create(workload->vgpu->gvt->dev_priv,
                                     roundup(ctx_size + CACHELINE_BYTES,
                                             PAGE_SIZE));
        if (IS_ERR(obj))
                goto unmap_src;
        }
 
-       ret = copy_gma_to_hva(wa_ctx->workload->vgpu,
-                               wa_ctx->workload->vgpu->gtt.ggtt_mm,
+       ret = copy_gma_to_hva(workload->vgpu,
+                               workload->vgpu->gtt.ggtt_mm,
                                guest_gma, guest_gma + ctx_size,
                                map);
        if (ret < 0) {
 int intel_gvt_scan_and_shadow_wa_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 {
        int ret;
-       struct intel_vgpu *vgpu = wa_ctx->workload->vgpu;
+       struct intel_vgpu_workload *workload = container_of(wa_ctx,
+                                       struct intel_vgpu_workload,
+                                       wa_ctx);
+       struct intel_vgpu *vgpu = workload->vgpu;
 
        if (wa_ctx->indirect_ctx.size == 0)
                return 0;
 
 
 static int update_wa_ctx_2_shadow_ctx(struct intel_shadow_wa_ctx *wa_ctx)
 {
-       int ring_id = wa_ctx->workload->ring_id;
-       struct i915_gem_context *shadow_ctx =
-               wa_ctx->workload->vgpu->shadow_ctx;
+       struct intel_vgpu_workload *workload = container_of(wa_ctx,
+                                       struct intel_vgpu_workload,
+                                       wa_ctx);
+       int ring_id = workload->ring_id;
+       struct i915_gem_context *shadow_ctx = workload->vgpu->shadow_ctx;
        struct drm_i915_gem_object *ctx_obj =
                shadow_ctx->engine[ring_id].state->obj;
        struct execlist_ring_context *shadow_ring_context;
                        CACHELINE_BYTES;
                workload->wa_ctx.per_ctx.guest_gma =
                        per_ctx & PER_CTX_ADDR_MASK;
-               workload->wa_ctx.workload = workload;
 
                WARN_ON(workload->wa_ctx.indirect_ctx.size && !(per_ctx & 0x1));
        }