riscv: dts: thead: change TH1520 uart nodes to use clock controller

Change the clock property in TH1520 uart nodes to a clock provided by
AP_SUBSYS clock controller.

Link: https://git.beagleboard.org/beaglev-ahead/beaglev-ahead/-/tree/main/docs
Signed-off-by: Drew Fustini <dfustini@tenstorrent.com>

diff --git a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
index b4d2e1d69bdb75337db46cb565d865f0c945b60a..90585883b0598b39f8ecdc244411d68bd997521b 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
+++ b/arch/riscv/boot/dts/thead/th1520-beaglev-ahead.dts
@@ -57,10 +57,6 @@
        clock-frequency = <396000000>;
 };
 
-&uart_sclk {
-       clock-frequency = <100000000>;
-};
-
 &dmac0 {
        status = "okay";
 };

diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
index 6939bd36560ca9220d840f7cb3e17970bf4af9d8..1c5c7075ae1744cec089eb91f611021a60f01a15 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
@@ -37,10 +37,6 @@
        clock-frequency = <396000000>;
 };
 
-&uart_sclk {
-       clock-frequency = <100000000>;
-};
-
 &dmac0 {
        status = "okay";
 };

diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index 25ef5ee729e608b27aa6fa634ed5d9058be86b9a..a543be8d6e378ea94ea8e86a42db5e70eb2fd0d7 100644 (file)
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -228,12 +228,6 @@
                #clock-cells = <0>;
        };
 
-       uart_sclk: uart-sclk-clock {
-               compatible = "fixed-clock";
-               clock-output-names = "uart_sclk";
-               #clock-cells = <0>;
-       };
-
        sdhci_clk: sdhci-clock {
                compatible = "fixed-clock";
                clock-frequency = <198000000>;
@@ -285,7 +279,8 @@
                        compatible = "snps,dw-apb-uart";
                        reg = <0xff 0xe7014000 0x0 0x100>;
                        interrupts = <36 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&uart_sclk>;
+                       clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART0_PCLK>;
+                       clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        status = "disabled";
@@ -322,7 +317,8 @@
                        compatible = "snps,dw-apb-uart";
                        reg = <0xff 0xe7f00000 0x0 0x100>;
                        interrupts = <37 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&uart_sclk>;
+                       clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART1_PCLK>;
+                       clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        status = "disabled";
@@ -332,7 +328,8 @@
                        compatible = "snps,dw-apb-uart";
                        reg = <0xff 0xe7f04000 0x0 0x100>;
                        interrupts = <39 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&uart_sclk>;
+                       clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART3_PCLK>;
+                       clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        status = "disabled";
@@ -414,7 +411,8 @@
                        compatible = "snps,dw-apb-uart";
                        reg = <0xff 0xec010000 0x0 0x4000>;
                        interrupts = <38 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&uart_sclk>;
+                       clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART2_PCLK>;
+                       clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        status = "disabled";
@@ -483,7 +481,8 @@
                        compatible = "snps,dw-apb-uart";
                        reg = <0xff 0xf7f08000 0x0 0x4000>;
                        interrupts = <40 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&uart_sclk>;
+                       clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART4_PCLK>;
+                       clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        status = "disabled";
@@ -493,7 +492,8 @@
                        compatible = "snps,dw-apb-uart";
                        reg = <0xff 0xf7f0c000 0x0 0x4000>;
                        interrupts = <41 IRQ_TYPE_LEVEL_HIGH>;
-                       clocks = <&uart_sclk>;
+                       clocks = <&clk CLK_UART_SCLK>, <&clk CLK_UART5_PCLK>;
+                       clock-names = "baudclk", "apb_pclk";
                        reg-shift = <2>;
                        reg-io-width = <4>;
                        status = "disabled";