if (HAS_PCH_SPLIT(dev_priv))
                sr_enabled = I915_READ(WM1_LP_ILK) & WM1_LP_SR_EN;
-       else if (IS_CRESTLINE(dev_priv) || IS_G4X(dev_priv) ||
+       else if (IS_I965GM(dev_priv) || IS_G4X(dev_priv) ||
                 IS_I945G(dev_priv) || IS_I945GM(dev_priv))
                sr_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
        else if (IS_I915GM(dev_priv))
 
         * behaviour if any general state is accessed within a page above 4GB,
         * which also needs to be handled carefully.
         */
-       if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv)) {
+       if (IS_I965G(dev_priv) || IS_I965GM(dev_priv)) {
                ret = dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(32));
 
                if (ret) {
 
        INTEL_I945GM,
        INTEL_G33,
        INTEL_PINEVIEW,
-       INTEL_BROADWATER,
-       INTEL_CRESTLINE,
+       INTEL_I965G,
+       INTEL_I965GM,
        INTEL_G4X,
        INTEL_IRONLAKE,
        INTEL_SANDYBRIDGE,
 #define IS_I915GM(dev_priv)    (INTEL_DEVID(dev_priv) == 0x2592)
 #define IS_I945G(dev_priv)     (INTEL_DEVID(dev_priv) == 0x2772)
 #define IS_I945GM(dev_priv)    ((dev_priv)->info.platform == INTEL_I945GM)
-#define IS_BROADWATER(dev_priv)        ((dev_priv)->info.platform == INTEL_BROADWATER)
-#define IS_CRESTLINE(dev_priv) ((dev_priv)->info.platform == INTEL_CRESTLINE)
+#define IS_I965G(dev_priv)     ((dev_priv)->info.platform == INTEL_I965G)
+#define IS_I965GM(dev_priv)    ((dev_priv)->info.platform == INTEL_I965GM)
 #define IS_GM45(dev_priv)      (INTEL_DEVID(dev_priv) == 0x2A42)
 #define IS_G4X(dev_priv)       ((dev_priv)->info.platform == INTEL_G4X)
 #define IS_PINEVIEW_G(dev_priv)        (INTEL_DEVID(dev_priv) == 0xa001)
 
                goto fail;
 
        mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
-       if (IS_CRESTLINE(dev_priv) || IS_BROADWATER(dev_priv)) {
+       if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
                /* 965gm cannot relocate objects above 4GiB. */
                mask &= ~__GFP_HIGHMEM;
                mask |= __GFP_DMA32;
 
 #endif
 
        gfp = GFP_KERNEL | __GFP_HIGHMEM | __GFP_RECLAIMABLE;
-       if (IS_CRESTLINE(i915) || IS_BROADWATER(i915)) {
+       if (IS_I965GM(i915) || IS_I965G(i915)) {
                /* 965gm cannot relocate objects above 4GiB. */
                gfp &= ~__GFP_HIGHMEM;
                gfp |= __GFP_DMA32;
 
 
 static const struct intel_device_info intel_i965g_info = {
        GEN4_FEATURES,
-       .platform = INTEL_BROADWATER,
+       .platform = INTEL_I965G,
        .has_overlay = 1,
        .hws_needs_physical = 1,
 };
 
 static const struct intel_device_info intel_i965gm_info = {
        GEN4_FEATURES,
-       .platform = INTEL_CRESTLINE,
+       .platform = INTEL_I965GM,
        .is_mobile = 1, .has_fbc = 1,
        .has_overlay = 1,
        .supports_tv = 1,
 
        PLATFORM_NAME(I945GM),
        PLATFORM_NAME(G33),
        PLATFORM_NAME(PINEVIEW),
-       PLATFORM_NAME(BROADWATER),
-       PLATFORM_NAME(CRESTLINE),
+       PLATFORM_NAME(I965G),
+       PLATFORM_NAME(I965GM),
        PLATFORM_NAME(G4X),
        PLATFORM_NAME(IRONLAKE),
        PLATFORM_NAME(SANDYBRIDGE),
 
 {
        if (INTEL_INFO(dev_priv)->gen >= 9)
                return 256 * 1024;
-       else if (IS_BROADWATER(dev_priv) || IS_CRESTLINE(dev_priv) ||
+       else if (IS_I965G(dev_priv) || IS_I965GM(dev_priv) ||
                 IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
                return 128 * 1024;
        else if (INTEL_INFO(dev_priv)->gen >= 4)
                vco_table = ctg_vco;
        else if (IS_G4X(dev_priv))
                vco_table = elk_vco;
-       else if (IS_CRESTLINE(dev_priv))
+       else if (IS_I965GM(dev_priv))
                vco_table = cl_vco;
        else if (IS_PINEVIEW(dev_priv))
                vco_table = pnv_vco;
        else if (IS_GEN5(dev_priv))
                dev_priv->display.get_display_clock_speed =
                        ilk_get_display_clock_speed;
-       else if (IS_I945G(dev_priv) || IS_BROADWATER(dev_priv) ||
+       else if (IS_I945G(dev_priv) || IS_I965G(dev_priv) ||
                 IS_GEN6(dev_priv) || IS_IVYBRIDGE(dev_priv))
                dev_priv->display.get_display_clock_speed =
                        i945_get_display_clock_speed;
        else if (IS_GM45(dev_priv))
                dev_priv->display.get_display_clock_speed =
                        gm45_get_display_clock_speed;
-       else if (IS_CRESTLINE(dev_priv))
+       else if (IS_I965GM(dev_priv))
                dev_priv->display.get_display_clock_speed =
                        i965gm_get_display_clock_speed;
        else if (IS_PINEVIEW(dev_priv))
 
                was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
                I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
                POSTING_READ(FW_BLC_SELF_VLV);
-       } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
+       } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) {
                was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN;
                I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
                POSTING_READ(FW_BLC_SELF);
                dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
        else if (IS_G4X(dev_priv))
                dev_priv->display.init_clock_gating = g4x_init_clock_gating;
-       else if (IS_CRESTLINE(dev_priv))
+       else if (IS_I965GM(dev_priv))
                dev_priv->display.init_clock_gating = crestline_init_clock_gating;
-       else if (IS_BROADWATER(dev_priv))
+       else if (IS_I965G(dev_priv))
                dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
        else if (IS_GEN3(dev_priv))
                dev_priv->display.init_clock_gating = gen3_init_clock_gating;