reg &= ~P_TXQ_PSM_VDD(port);
        core_writel(priv, reg, CORE_MEM_PSM_VDD_CTRL);
 
+       /* Enable learning */
+       reg = core_readl(priv, CORE_DIS_LEARN);
+       reg &= ~BIT(port);
+       core_writel(priv, reg, CORE_DIS_LEARN);
+
        /* Enable Broadcom tags for that port if requested */
        if (priv->brcm_tag_mask & BIT(port))
                b53_brcm_hdr_setup(ds, port);
        struct bcm_sf2_priv *priv = bcm_sf2_to_priv(ds);
        u32 reg;
 
-       if (priv->wol_ports_mask & (1 << port))
+       /* Disable learning while in WoL mode */
+       if (priv->wol_ports_mask & (1 << port)) {
+               reg = core_readl(priv, CORE_DIS_LEARN);
+               reg |= BIT(port);
+               core_writel(priv, reg, CORE_DIS_LEARN);
                return;
+       }
 
        if (port == priv->moca_port)
                bcm_sf2_port_intr_disable(priv, port);
 
 #define CORE_SWITCH_CTRL               0x00088
 #define  MII_DUMB_FWDG_EN              (1 << 6)
 
+#define CORE_DIS_LEARN                 0x000f0
+
 #define CORE_SFT_LRN_CTRL              0x000f8
 #define  SW_LEARN_CNTL(x)              (1 << (x))