Required properties:
  
  - compatible : should be one of
+       "apm,potenza-pmu"
        "arm,armv8-pmuv3"
 +      "arm.cortex-a57-pmu"
 +      "arm.cortex-a53-pmu"
        "arm,cortex-a17-pmu"
        "arm,cortex-a15-pmu"
        "arm,cortex-a12-pmu"
 
  - interrupt-parent: Specifies the phandle of the interrupt controller to which
    the interrupts from s2mps11 are delivered to.
  - interrupts: Interrupt specifiers for interrupt sources.
 +- samsung,s2mps11-wrstbi-ground: Indicates that WRSTBI pin of PMIC is pulled
 +  down. When the system is suspended it will always go down thus triggerring
 +  unwanted buck warm reset (setting buck voltages to default values).
+ - samsung,s2mps11-acokb-ground: Indicates that ACOKB pin of S2MPS11 PMIC is
+   connected to the ground so the PMIC must manually set PWRHOLD bit in CTRL1
+   register to turn off the power. Usually the ACOKB is pulled up to VBATT so
+   when PWRHOLD pin goes low, the rising ACOKB will trigger power off.
  
  Optional nodes:
 -- clocks: s2mps11, s2mps13 and s5m8767 provide three(AP/CP/BT) buffered 32.768
 +- clocks: s2mps11, s2mps13, s2mps15 and s5m8767 provide three(AP/CP/BT) buffered 32.768
    KHz outputs, so to register these as clocks with common clock framework
    instantiate a sub-node named "clocks". It uses the common clock binding
    documented in :
 
  phytec        PHYTEC Messtechnik GmbH
  picochip      Picochip Ltd
  plathome      Plat'Home Co., Ltd.
+ plda  PLDA
  pixcir  PIXCIR MICROELECTRONICS Co., Ltd
 +pulsedlight   PulsedLight, Inc
  powervr       PowerVR (deprecated, use img)
  qca   Qualcomm Atheros, Inc.
  qcom  Qualcomm Technologies, Inc
  toshiba       Toshiba Corporation
  toumaz        Toumaz
  tplink        TP-LINK Technologies Co., Ltd.
+ tronfy        Tronfy
  truly Truly Semiconductors Limited
 +upisemi       uPI Semiconductor Corp.
  usi   Universal Scientific Industrial Co., Ltd.
  v3    V3 Semiconductor
  variscite     Variscite Ltd.
 
                                status = "disabled";
                        };
  
 +                      pioA: pinctrl@fc038000 {
 +                              compatible = "atmel,sama5d2-pinctrl";
 +                              reg = <0xfc038000 0x600>;
 +                              interrupts = <18 IRQ_TYPE_LEVEL_HIGH 7>,
 +                                           <68 IRQ_TYPE_LEVEL_HIGH 7>,
 +                                           <69 IRQ_TYPE_LEVEL_HIGH 7>,
 +                                           <70 IRQ_TYPE_LEVEL_HIGH 7>;
 +                              interrupt-controller;
 +                              #interrupt-cells = <2>;
 +                              gpio-controller;
 +                              #gpio-cells = <2>;
 +                              clocks = <&pioA_clk>;
 +                      };
++
+                       tdes@fc044000 {
+                               compatible = "atmel,at91sam9g46-tdes";
+                               reg = <0xfc044000 0x100>;
+                               interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
+                               dmas = <&dma0
+                                       (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+                                        AT91_XDMAC_DT_PERID(28))>,
+                                      <&dma0
+                                       (AT91_XDMAC_DT_MEM_IF(0) | AT91_XDMAC_DT_PER_IF(1) |
+                                        AT91_XDMAC_DT_PERID(29))>;
+                               dma-names = "tx", "rx";
+                               clocks = <&tdes_clk>;
+                               clock-names = "tdes_clk";
+                               status = "okay";
+                       };
                };
        };
  };
 
                        clock-names     = "pwm";
                        clocks          = <&clk_sysin>;
                        st,pwm-num-chan = <4>;
+ 
+                       status          = "disabled";
+               };
+ 
+               rng10: rng@08a89000 {
+                       compatible      = "st,rng";
+                       reg             = <0x08a89000 0x1000>;
+                       clocks          = <&clk_sysin>;
+                       status          = "okay";
+               };
+ 
+               rng11: rng@08a8a000 {
+                       compatible      = "st,rng";
+                       reg             = <0x08a8a000 0x1000>;
+                       clocks          = <&clk_sysin>;
+                       status          = "okay";
+               };
+ 
+               ethernet0: dwmac@9630000 {
+                       device_type = "network";
+                       status = "disabled";
+                       compatible = "st,stih407-dwmac", "snps,dwmac", "snps,dwmac-3.710";
+                       reg = <0x9630000 0x8000>, <0x80 0x4>;
+                       reg-names = "stmmaceth", "sti-ethconf";
+ 
+                       st,syscon = <&syscfg_sbc_reg 0x80>;
+                       st,gmac_en;
+                       resets = <&softreset STIH407_ETH1_SOFTRESET>;
+                       reset-names = "stmmaceth";
+ 
+                       interrupts = <GIC_SPI 98 IRQ_TYPE_NONE>,
+                                    <GIC_SPI 99 IRQ_TYPE_NONE>;
+                       interrupt-names = "macirq", "eth_wake_irq";
+ 
+                       /* DMA Bus Mode */
+                       snps,pbl = <8>;
+ 
+                       pinctrl-names = "default";
+                       pinctrl-0 = <&pinctrl_rgmii1>;
+ 
+                       clock-names = "stmmaceth", "sti-ethclk";
+                       clocks = <&clk_s_c0_flexgen CLK_EXT2F_A9>,
+                                <&clk_s_c0_flexgen CLK_ETH_PHY>;
                };
 +
 +              rng10: rng@08a89000 {
 +                      compatible      = "st,rng";
 +                      reg             = <0x08a89000 0x1000>;
 +                      clocks          = <&clk_sysin>;
 +                      status          = "okay";
 +              };
 +
 +              rng11: rng@08a8a000 {
 +                      compatible      = "st,rng";
 +                      reg             = <0x08a8a000 0x1000>;
 +                      clocks          = <&clk_sysin>;
 +                      status          = "okay";
 +              };
        };
  };
 
  CONFIG_ARCH_ZYNQMP=y
  CONFIG_PCI=y
  CONFIG_PCI_MSI=y
+ CONFIG_PCI_HOST_GENERIC=y
  CONFIG_PCI_XGENE=y
  CONFIG_SMP=y
 +CONFIG_SCHED_MC=y
  CONFIG_PREEMPT=y
  CONFIG_KSM=y
  CONFIG_TRANSPARENT_HUGEPAGE=y