MLX5_CQ_PERIOD_MODE_START_FROM_CQE :
                                         MLX5_CQ_PERIOD_MODE_START_FROM_EQE;
  
-       params->log_sq_size = MLX5E_PARAMS_MINIMUM_LOG_SQ_SIZE;
 +      params->hard_mtu    = MLX5E_ETH_HARD_MTU;
+       params->log_sq_size = MLX5E_REP_PARAMS_LOG_SQ_SIZE;
        params->rq_wq_type  = MLX5_WQ_TYPE_LINKED_LIST;
-       params->log_rq_mtu_frames = MLX5E_PARAMS_MINIMUM_LOG_RQ_SIZE;
 -      params->log_rq_size = MLX5E_REP_PARAMS_LOG_RQ_SIZE;
++      params->log_rq_mtu_frames = MLX5E_REP_PARAMS_LOG_RQ_SIZE;
  
        params->rx_dim_enabled = MLX5_CAP_GEN(mdev, cq_moderation);
        mlx5e_set_rx_cq_mode_params(params, cq_period_mode);
 
        if (rc < 0)
                return rc;
  
-       pci_set_drvdata(pdev, dev);
- 
        netif_info(tp, probe, dev, "%s at 0x%p, %pM, XID %08x IRQ %d\n",
 -                 rtl_chip_infos[chipset].name, ioaddr, dev->dev_addr,
 -                 (u32)(RTL_R32(TxConfig) & 0x9cf0f8ff), pdev->irq);
 +                 rtl_chip_infos[chipset].name, tp->mmio_addr, dev->dev_addr,
 +                 (u32)(RTL_R32(tp, TxConfig) & 0x9cf0f8ff),
 +                 pci_irq_vector(pdev, 0));
        if (rtl_chip_infos[chipset].jumbo_max != JUMBO_1K) {
                netif_info(tp, probe, dev, "jumbo features [frames: %d bytes, "
                           "tx checksumming: %s]\n",
 
        struct ip_tunnel *nt;
        struct net_device *dev;
        int t_hlen;
+       int mtu;
+       int err;
  
 -      BUG_ON(!itn->fb_tunnel_dev);
 -      dev = __ip_tunnel_create(net, itn->fb_tunnel_dev->rtnl_link_ops, parms);
 +      dev = __ip_tunnel_create(net, itn->rtnl_link_ops, parms);
        if (IS_ERR(dev))
                return ERR_CAST(dev);