drm/amdgpu/display/dm: convert to IP version checking

Use IP versions rather than asic_type to differentiate
IP version specific features.

v2: drop unrelated change

Acked-by: Christian König <christian.koenig@amd.com> (v1)
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 3c7a8f869b40f830bcfb993f535f9fbafa2f9d01..1aa34838ecd1706ed6add1e8243cf6f92fa3153e 100644 (file)
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -1343,19 +1343,26 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
        case CHIP_CARRIZO:
        case CHIP_STONEY:
        case CHIP_RAVEN:
-       case CHIP_RENOIR:
-               init_data.flags.gpu_vm_support = true;
-               if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
-                       init_data.flags.disable_dmcu = true;
-               break;
-       case CHIP_VANGOGH:
-       case CHIP_YELLOW_CARP:
                init_data.flags.gpu_vm_support = true;
                break;
-       case CHIP_CYAN_SKILLFISH:
-               init_data.flags.disable_dmcu = true;
-               break;
        default:
+               switch (adev->ip_versions[DCE_HWIP]) {
+               case IP_VERSION(2, 1, 0):
+                       init_data.flags.gpu_vm_support = true;
+                       if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
+                               init_data.flags.disable_dmcu = true;
+                       break;
+               case IP_VERSION(3, 0, 1):
+               case IP_VERSION(3, 1, 2):
+               case IP_VERSION(3, 1, 3):
+                       init_data.flags.gpu_vm_support = true;
+                       break;
+               case IP_VERSION(2, 0, 3):
+                       init_data.flags.disable_dmcu = true;
+                       break;
+               default:
+                       break;
+               }
                break;
        }
 
@@ -1446,7 +1453,7 @@ static int amdgpu_dm_init(struct amdgpu_device *adev)
 #endif
 
 #ifdef CONFIG_DRM_AMD_DC_HDCP
-       if (adev->dm.dc->caps.max_links > 0 && adev->asic_type >= CHIP_RAVEN) {
+       if (adev->dm.dc->caps.max_links > 0 && adev->family >= AMDGPU_FAMILY_RV) {
                adev->dm.hdcp_workqueue = hdcp_create_workqueue(adev, &init_params.cp_psp, adev->dm.dc);
 
                if (!adev->dm.hdcp_workqueue)
@@ -1641,16 +1648,6 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
        case CHIP_VEGA10:
        case CHIP_VEGA12:
        case CHIP_VEGA20:
-       case CHIP_NAVI10:
-       case CHIP_NAVI14:
-       case CHIP_RENOIR:
-       case CHIP_SIENNA_CICHLID:
-       case CHIP_NAVY_FLOUNDER:
-       case CHIP_DIMGREY_CAVEFISH:
-       case CHIP_BEIGE_GOBY:
-       case CHIP_VANGOGH:
-       case CHIP_YELLOW_CARP:
-       case CHIP_CYAN_SKILLFISH:
                return 0;
        case CHIP_NAVI12:
                fw_name_dmcu = FIRMWARE_NAVI12_DMCU;
@@ -1664,6 +1661,21 @@ static int load_dmcu_fw(struct amdgpu_device *adev)
                        return 0;
                break;
        default:
+               switch (adev->ip_versions[DCE_HWIP]) {
+               case IP_VERSION(2, 0, 2):
+               case IP_VERSION(2, 0, 3):
+               case IP_VERSION(2, 0, 0):
+               case IP_VERSION(2, 1, 0):
+               case IP_VERSION(3, 0, 0):
+               case IP_VERSION(3, 0, 2):
+               case IP_VERSION(3, 0, 3):
+               case IP_VERSION(3, 0, 1):
+               case IP_VERSION(3, 1, 2):
+               case IP_VERSION(3, 1, 3):
+                       return 0;
+               default:
+                       break;
+               }
                DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
                return -EINVAL;
        }
@@ -1742,34 +1754,36 @@ static int dm_dmub_sw_init(struct amdgpu_device *adev)
        enum dmub_status status;
        int r;
 
-       switch (adev->asic_type) {
-       case CHIP_RENOIR:
+       switch (adev->ip_versions[DCE_HWIP]) {
+       case IP_VERSION(2, 1, 0):
                dmub_asic = DMUB_ASIC_DCN21;
                fw_name_dmub = FIRMWARE_RENOIR_DMUB;
                if (ASICREV_IS_GREEN_SARDINE(adev->external_rev_id))
                        fw_name_dmub = FIRMWARE_GREEN_SARDINE_DMUB;
                break;
-       case CHIP_SIENNA_CICHLID:
-               dmub_asic = DMUB_ASIC_DCN30;
-               fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
-               break;
-       case CHIP_NAVY_FLOUNDER:
-               dmub_asic = DMUB_ASIC_DCN30;
-               fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
+       case IP_VERSION(3, 0, 0):
+               if (adev->ip_versions[GC_HWIP] == IP_VERSION(10, 3, 0)) {
+                       dmub_asic = DMUB_ASIC_DCN30;
+                       fw_name_dmub = FIRMWARE_SIENNA_CICHLID_DMUB;
+               } else {
+                       dmub_asic = DMUB_ASIC_DCN30;
+                       fw_name_dmub = FIRMWARE_NAVY_FLOUNDER_DMUB;
+               }
                break;
-       case CHIP_VANGOGH:
+       case IP_VERSION(3, 0, 1):
                dmub_asic = DMUB_ASIC_DCN301;
                fw_name_dmub = FIRMWARE_VANGOGH_DMUB;
                break;
-       case CHIP_DIMGREY_CAVEFISH:
+       case IP_VERSION(3, 0, 2):
                dmub_asic = DMUB_ASIC_DCN302;
                fw_name_dmub = FIRMWARE_DIMGREY_CAVEFISH_DMUB;
                break;
-       case CHIP_BEIGE_GOBY:
+       case IP_VERSION(3, 0, 3):
                dmub_asic = DMUB_ASIC_DCN303;
                fw_name_dmub = FIRMWARE_BEIGE_GOBY_DMUB;
                break;
-       case CHIP_YELLOW_CARP:
+       case IP_VERSION(3, 1, 2):
+       case IP_VERSION(3, 1, 3):
                dmub_asic = DMUB_ASIC_DCN31;
                fw_name_dmub = FIRMWARE_YELLOW_CARP_DMUB;
                break;
@@ -2069,10 +2083,9 @@ static int amdgpu_dm_smu_write_watermarks_table(struct amdgpu_device *adev)
         * therefore, this function apply to navi10/12/14 but not Renoir
         * *
         */
-       switch(adev->asic_type) {
-       case CHIP_NAVI10:
-       case CHIP_NAVI14:
-       case CHIP_NAVI12:
+       switch (adev->ip_versions[DCE_HWIP]) {
+       case IP_VERSION(2, 0, 2):
+       case IP_VERSION(2, 0, 0):
                break;
        default:
                return 0;
@@ -3293,7 +3306,7 @@ static int dce110_register_irq_handlers(struct amdgpu_device *adev)
        int i;
        unsigned client_id = AMDGPU_IRQ_CLIENTID_LEGACY;
 
-       if (adev->asic_type >= CHIP_VEGA10)
+       if (adev->family >= AMDGPU_FAMILY_AI)
                client_id = SOC15_IH_CLIENTID_DCE;
 
        int_params.requested_polarity = INTERRUPT_POLARITY_DEFAULT;
@@ -4078,18 +4091,19 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
 
 #if defined(CONFIG_DRM_AMD_DC_DCN)
        /* Use Outbox interrupt */
-       switch (adev->asic_type) {
-       case CHIP_SIENNA_CICHLID:
-       case CHIP_NAVY_FLOUNDER:
-       case CHIP_YELLOW_CARP:
-       case CHIP_RENOIR:
+       switch (adev->ip_versions[DCE_HWIP]) {
+       case IP_VERSION(3, 0, 0):
+       case IP_VERSION(3, 1, 2):
+       case IP_VERSION(3, 1, 3):
+       case IP_VERSION(2, 1, 0):
                if (register_outbox_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
                        goto fail;
                }
                break;
        default:
-               DRM_DEBUG_KMS("Unsupported ASIC type for outbox: 0x%X\n", adev->asic_type);
+               DRM_DEBUG_KMS("Unsupported DCN IP version for outbox: 0x%X\n",
+                             adev->ip_versions[DCE_HWIP]);
        }
 #endif
 
@@ -4177,17 +4191,6 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
                break;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
        case CHIP_RAVEN:
-       case CHIP_NAVI12:
-       case CHIP_NAVI10:
-       case CHIP_NAVI14:
-       case CHIP_RENOIR:
-       case CHIP_SIENNA_CICHLID:
-       case CHIP_NAVY_FLOUNDER:
-       case CHIP_DIMGREY_CAVEFISH:
-       case CHIP_BEIGE_GOBY:
-       case CHIP_VANGOGH:
-       case CHIP_CYAN_SKILLFISH:
-       case CHIP_YELLOW_CARP:
                if (dcn10_register_irq_handlers(dm->adev)) {
                        DRM_ERROR("DM: Failed to initialize IRQ\n");
                        goto fail;
@@ -4195,6 +4198,27 @@ static int amdgpu_dm_initialize_drm_device(struct amdgpu_device *adev)
                break;
 #endif
        default:
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+               switch (adev->ip_versions[DCE_HWIP]) {
+               case IP_VERSION(2, 0, 2):
+               case IP_VERSION(2, 0, 3):
+               case IP_VERSION(2, 0, 0):
+               case IP_VERSION(2, 1, 0):
+               case IP_VERSION(3, 0, 0):
+               case IP_VERSION(3, 0, 2):
+               case IP_VERSION(3, 0, 3):
+               case IP_VERSION(3, 0, 1):
+               case IP_VERSION(3, 1, 2):
+               case IP_VERSION(3, 1, 3):
+                       if (dcn10_register_irq_handlers(dm->adev)) {
+                               DRM_ERROR("DM: Failed to initialize IRQ\n");
+                               goto fail;
+                       }
+                       break;
+               default:
+                       break;
+               }
+#endif
                DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
                goto fail;
        }
@@ -4345,43 +4369,44 @@ static int dm_early_init(void *handle)
                break;
 #if defined(CONFIG_DRM_AMD_DC_DCN)
        case CHIP_RAVEN:
-       case CHIP_RENOIR:
-       case CHIP_VANGOGH:
-               adev->mode_info.num_crtc = 4;
-               adev->mode_info.num_hpd = 4;
-               adev->mode_info.num_dig = 4;
-               break;
-       case CHIP_NAVI10:
-       case CHIP_NAVI12:
-       case CHIP_SIENNA_CICHLID:
-       case CHIP_NAVY_FLOUNDER:
-               adev->mode_info.num_crtc = 6;
-               adev->mode_info.num_hpd = 6;
-               adev->mode_info.num_dig = 6;
-               break;
-       case CHIP_YELLOW_CARP:
                adev->mode_info.num_crtc = 4;
                adev->mode_info.num_hpd = 4;
                adev->mode_info.num_dig = 4;
                break;
-       case CHIP_CYAN_SKILLFISH:
-               adev->mode_info.num_crtc = 2;
-               adev->mode_info.num_hpd = 2;
-               adev->mode_info.num_dig = 2;
-               break;
-       case CHIP_NAVI14:
-       case CHIP_DIMGREY_CAVEFISH:
-               adev->mode_info.num_crtc = 5;
-               adev->mode_info.num_hpd = 5;
-               adev->mode_info.num_dig = 5;
-               break;
-       case CHIP_BEIGE_GOBY:
-               adev->mode_info.num_crtc = 2;
-               adev->mode_info.num_hpd = 2;
-               adev->mode_info.num_dig = 2;
-               break;
 #endif
        default:
+#if defined(CONFIG_DRM_AMD_DC_DCN)
+               switch (adev->ip_versions[DCE_HWIP]) {
+               case IP_VERSION(2, 0, 2):
+               case IP_VERSION(3, 0, 0):
+                       adev->mode_info.num_crtc = 6;
+                       adev->mode_info.num_hpd = 6;
+                       adev->mode_info.num_dig = 6;
+                       break;
+               case IP_VERSION(2, 0, 0):
+               case IP_VERSION(3, 0, 2):
+                       adev->mode_info.num_crtc = 5;
+                       adev->mode_info.num_hpd = 5;
+                       adev->mode_info.num_dig = 5;
+                       break;
+               case IP_VERSION(2, 0, 3):
+               case IP_VERSION(3, 0, 3):
+                       adev->mode_info.num_crtc = 2;
+                       adev->mode_info.num_hpd = 2;
+                       adev->mode_info.num_dig = 2;
+                       break;
+               case IP_VERSION(3, 0, 1):
+               case IP_VERSION(2, 1, 0):
+               case IP_VERSION(3, 1, 2):
+               case IP_VERSION(3, 1, 3):
+                       adev->mode_info.num_crtc = 4;
+                       adev->mode_info.num_hpd = 4;
+                       adev->mode_info.num_dig = 4;
+                       break;
+               default:
+                       break;
+               }
+#endif
                DRM_ERROR("Unsupported ASIC type: 0x%X\n", adev->asic_type);
                return -EINVAL;
        }
@@ -4602,12 +4627,7 @@ fill_gfx9_tiling_info_from_device(const struct amdgpu_device *adev,
        tiling_info->gfx9.num_rb_per_se =
                adev->gfx.config.gb_addr_config_fields.num_rb_per_se;
        tiling_info->gfx9.shaderEnable = 1;
-       if (adev->asic_type == CHIP_SIENNA_CICHLID ||
-           adev->asic_type == CHIP_NAVY_FLOUNDER ||
-           adev->asic_type == CHIP_DIMGREY_CAVEFISH ||
-           adev->asic_type == CHIP_BEIGE_GOBY ||
-           adev->asic_type == CHIP_YELLOW_CARP ||
-           adev->asic_type == CHIP_VANGOGH)
+       if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
                tiling_info->gfx9.num_pkrs = adev->gfx.config.gb_addr_config_fields.num_pkrs;
 }
 
@@ -5048,7 +5068,7 @@ get_plane_modifiers(const struct amdgpu_device *adev, unsigned int plane_type, u
        case AMDGPU_FAMILY_NV:
        case AMDGPU_FAMILY_VGH:
        case AMDGPU_FAMILY_YC:
-               if (adev->asic_type >= CHIP_SIENNA_CICHLID)
+               if (adev->ip_versions[GC_HWIP] >= IP_VERSION(10, 3, 0))
                        add_gfx10_3_modifiers(adev, mods, &size, &capacity);
                else
                        add_gfx10_1_modifiers(adev, mods, &size, &capacity);