arm64: dts: blaize-blzp1600: Enable GPIO support

Blaize BLZP1600 uses the custom silicon provided from
VeriSilicon to add GPIO support.
This interface is used to control signals on many other
peripherals, such as Ethernet, USB, SD and eMMC.

Signed-off-by: Nikolaos Pasaloukos <nikolaos.pasaloukos@blaize.com>
Link: https://lore.kernel.org/r/20250512133302.151621-1-nikolaos.pasaloukos@blaize.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>

diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
index 7e3cef2ed3522e202487e799b2021cd45398e006..fb5415eb347a028fc65090027a4c4fc89c8280f5 100644 (file)
--- a/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600-cb2.dts
@@ -81,3 +81,39 @@
                                  "UART1_TO_RSP";       /* GPIO_15 */
        };
 };
+
+&gpio0 {
+       status = "okay";
+       gpio-line-names = "PERST_N",            /* GPIO_0 */
+                         "LM96063_ALERT_N",    /* GPIO_1 */
+                         "INA3221_PV",         /* GPIO_2 */
+                         "INA3221_CRIT",       /* GPIO_3 */
+                         "INA3221_WARN",       /* GPIO_4 */
+                         "INA3221_TC",         /* GPIO_5 */
+                         "QSPI0_RST_N",        /* GPIO_6 */
+                         "LM96063_TCRIT_N",    /* GPIO_7 */
+                         "DSI_TCH_INT",        /* GPIO_8 */
+                         "DSI_RST",            /* GPIO_9 */
+                         "DSI_BL",             /* GPIO_10 */
+                         "DSI_INT",            /* GPIO_11 */
+                         "ETH_RST",            /* GPIO_12 */
+                         "CSI0_RST",           /* GPIO_13 */
+                         "CSI0_PWDN",          /* GPIO_14 */
+                         "CSI1_RST",           /* GPIO_15 */
+                         "CSI1_PWDN",          /* GPIO_16 */
+                         "CSI2_RST",           /* GPIO_17 */
+                         "CSI2_PWDN",          /* GPIO_18 */
+                         "CSI3_RST",           /* GPIO_19 */
+                         "CSI3_PWDN",          /* GPIO_20 */
+                         "ADAC_RST",           /* GPIO_21 */
+                         "SD_SW_VDD",          /* GPIO_22 */
+                         "SD_PON_VDD",         /* GPIO_23 */
+                         "GPIO_EXP_INT",       /* GPIO_24 */
+                         "BOARD_ID_0",         /* GPIO_25 */
+                         "SDIO1_SW_VDD",       /* GPIO_26 */
+                         "SDIO1_PON_VDD",      /* GPIO_27 */
+                         "SDIO2_SW_VDD",       /* GPIO_28 */
+                         "SDIO2_PON_VDD",      /* GPIO_29 */
+                         "BOARD_ID_1",         /* GPIO_30 */
+                         "BOARD_ID_2";         /* GPIO_31 */
+};

diff --git a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
index 7d399e6a532f5b24385dd837be965be771c7d24c..5a6c882b2f57d57d304869dee877c996cbabb712 100644 (file)
--- a/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
+++ b/arch/arm64/boot/dts/blaize/blaize-blzp1600.dtsi
@@ -120,6 +120,18 @@
                                                 IRQ_TYPE_LEVEL_LOW)>;
                };
 
+               gpio0: gpio@4c0000 {
+                       compatible = "blaize,blzp1600-gpio";
+                       reg = <0x4c0000 0x1000>;
+                       gpio-controller;
+                       #gpio-cells = <2>;
+                       ngpios = <32>;
+                       interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
+                       interrupt-controller;
+                       #interrupt-cells = <2>;
+                       status = "disabled";
+               };
+
                uart0: serial@4d0000 {
                        compatible = "ns16550a";
                        reg = <0x4d0000 0x1000>;