This patch adds CSI subnodes for IPU1 and IPU2 that will contain
ports and endpoints connecting to external elements in the video
pipeline.
Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
                        clock-names = "bus", "di0", "di1";
                        resets = <&src 4>;
 
+                       ipu2_csi0: port@0 {
+                               reg = <0>;
+                       };
+
+                       ipu2_csi1: port@1 {
+                               reg = <1>;
+                       };
+
                        ipu2_di0: port@2 {
                                #address-cells = <1>;
                                #size-cells = <0>;
 
                        clock-names = "bus", "di0", "di1";
                        resets = <&src 2>;
 
+                       ipu1_csi0: port@0 {
+                               reg = <0>;
+                       };
+
+                       ipu1_csi1: port@1 {
+                               reg = <1>;
+                       };
+
                        ipu1_di0: port@2 {
                                #address-cells = <1>;
                                #size-cells = <0>;