phy: qcom: qmp: move common bits definitions to common header

Move bit definitions for the common headers to the common phy-qcom-qmp.h
header.

Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Link: https://lore.kernel.org/r/20240126-phy-qmp-merge-common-v2-5-a463d0b57836@linaro.org
Signed-off-by: Vinod Koul <vkoul@kernel.org>

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
index bb961094e41a66e13989a9eafa41aa109ef6a3bb..b6908a03da58663d197297e6be8729ea01a73b17 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-combo.c
@@ -41,16 +41,6 @@
 #include "phy-qcom-qmp-dp-phy-v5.h"
 #include "phy-qcom-qmp-dp-phy-v6.h"
 
-/* QPHY_SW_RESET bit */
-#define SW_RESET                               BIT(0)
-/* QPHY_POWER_DOWN_CONTROL */
-#define SW_PWRDN                               BIT(0)
-/* QPHY_START_CONTROL bits */
-#define SERDES_START                           BIT(0)
-#define PCS_START                              BIT(1)
-/* QPHY_PCS_STATUS bit */
-#define PHYSTATUS                              BIT(6)
-
 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
 /* DP PHY soft reset */
 #define SW_DPPHY_RESET                         BIT(0)
@@ -65,17 +55,6 @@
 #define USB3_MODE                              BIT(0) /* enables USB3 mode */
 #define DP_MODE                                        BIT(1) /* enables DP mode */
 
-/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-#define ARCVR_DTCT_EN                          BIT(0)
-#define ALFPS_DTCT_EN                          BIT(1)
-#define ARCVR_DTCT_EVENT_SEL                   BIT(4)
-
-/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-#define IRQ_CLEAR                              BIT(0)
-
-/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-#define CLAMP_EN                               BIT(0) /* enables i/o clamp_n */
-
 /* QPHY_V3_DP_COM_TYPEC_CTRL register bits */
 #define SW_PORTSELECT_VAL                      BIT(0)
 #define SW_PORTSELECT_MUX                      BIT(1)

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
index 07c6f20a49d43e8cb7ebdd0321c82479c5a4ad45..0442b31205638cdea16694e256c86e436a3186e6 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie-msm8996.c
@@ -23,17 +23,9 @@
 
 #include "phy-qcom-qmp.h"
 
-/* QPHY_SW_RESET bit */
-#define SW_RESET                               BIT(0)
-/* QPHY_POWER_DOWN_CONTROL */
-#define SW_PWRDN                               BIT(0)
-#define REFCLK_DRV_DSBL                                BIT(1)
 /* QPHY_START_CONTROL bits */
-#define SERDES_START                           BIT(0)
-#define PCS_START                              BIT(1)
 #define PLL_READY_GATE_EN                      BIT(3)
-/* QPHY_PCS_STATUS bit */
-#define PHYSTATUS                              BIT(6)
+
 /* QPHY_COM_PCS_READY_STATUS bit */
 #define PCS_READY                              BIT(0)
 

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
index a4c8b6e9a7df888a40fbbebbd0c3d3af3dc01761..8836bb1ff0cc1ee31b7778b23f7a5c766091a67c 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
@@ -34,18 +34,6 @@
 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
 #include "phy-qcom-qmp-pcie-qhp.h"
 
-/* QPHY_SW_RESET bit */
-#define SW_RESET                               BIT(0)
-/* QPHY_POWER_DOWN_CONTROL */
-#define SW_PWRDN                               BIT(0)
-#define REFCLK_DRV_DSBL                                BIT(1)
-/* QPHY_START_CONTROL bits */
-#define SERDES_START                           BIT(0)
-#define PCS_START                              BIT(1)
-/* QPHY_PCS_STATUS bit */
-#define PHYSTATUS                              BIT(6)
-#define PHYSTATUS_4_20                         BIT(7)
-
 #define PHY_INIT_COMPLETE_TIMEOUT              10000
 
 /* set of registers with offsets different per-PHY */

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
index 01a96c60c9136e84742da696cc8ce5653cec5ada..38c4a4cc670a78c8c108a669db7a0b92b392baee 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
@@ -32,13 +32,6 @@
 
 #include "phy-qcom-qmp-qserdes-txrx-ufs-v6.h"
 
-/* QPHY_SW_RESET bit */
-#define SW_RESET                               BIT(0)
-/* QPHY_POWER_DOWN_CONTROL */
-#define SW_PWRDN                               BIT(0)
-/* QPHY_START_CONTROL bits */
-#define SERDES_START                           BIT(0)
-#define PCS_START                              BIT(1)
 /* QPHY_PCS_READY_STATUS bit */
 #define PCS_READY                              BIT(0)
 

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
index ca220878c63005b736680f49f30314b2d13c1ebe..6d0ba39c19431e103f0c92d24b79615bdc7d1828 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb-legacy.c
@@ -27,16 +27,6 @@
 
 #include "phy-qcom-qmp-dp-com-v3.h"
 
-/* QPHY_SW_RESET bit */
-#define SW_RESET                               BIT(0)
-/* QPHY_POWER_DOWN_CONTROL */
-#define SW_PWRDN                               BIT(0)
-/* QPHY_START_CONTROL bits */
-#define SERDES_START                           BIT(0)
-#define PCS_START                              BIT(1)
-/* QPHY_PCS_STATUS bit */
-#define PHYSTATUS                              BIT(6)
-
 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
 /* DP PHY soft reset */
 #define SW_DPPHY_RESET                         BIT(0)
@@ -51,17 +41,6 @@
 #define USB3_MODE                              BIT(0) /* enables USB3 mode */
 #define DP_MODE                                        BIT(1) /* enables DP mode */
 
-/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-#define ARCVR_DTCT_EN                          BIT(0)
-#define ALFPS_DTCT_EN                          BIT(1)
-#define ARCVR_DTCT_EVENT_SEL                   BIT(4)
-
-/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-#define IRQ_CLEAR                              BIT(0)
-
-/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-#define CLAMP_EN                               BIT(0) /* enables i/o clamp_n */
-
 #define PHY_INIT_COMPLETE_TIMEOUT              10000
 
 struct qmp_phy_init_tbl {

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
index a4d2bb3ae6059392de936caa68641ca06db27c7e..6b6994cb77d73f334fbb531850e260a60b6697ba 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usb.c
@@ -29,41 +29,6 @@
 #include "phy-qcom-qmp-pcs-usb-v6.h"
 #include "phy-qcom-qmp-pcs-usb-v7.h"
 
-/* QPHY_SW_RESET bit */
-#define SW_RESET                               BIT(0)
-/* QPHY_POWER_DOWN_CONTROL */
-#define SW_PWRDN                               BIT(0)
-/* QPHY_START_CONTROL bits */
-#define SERDES_START                           BIT(0)
-#define PCS_START                              BIT(1)
-/* QPHY_PCS_STATUS bit */
-#define PHYSTATUS                              BIT(6)
-
-/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-/* DP PHY soft reset */
-#define SW_DPPHY_RESET                         BIT(0)
-/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-#define SW_DPPHY_RESET_MUX                     BIT(1)
-/* USB3 PHY soft reset */
-#define SW_USB3PHY_RESET                       BIT(2)
-/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-#define SW_USB3PHY_RESET_MUX                   BIT(3)
-
-/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-#define USB3_MODE                              BIT(0) /* enables USB3 mode */
-#define DP_MODE                                        BIT(1) /* enables DP mode */
-
-/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-#define ARCVR_DTCT_EN                          BIT(0)
-#define ALFPS_DTCT_EN                          BIT(1)
-#define ARCVR_DTCT_EVENT_SEL                   BIT(4)
-
-/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-#define IRQ_CLEAR                              BIT(0)
-
-/* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
-#define CLAMP_EN                               BIT(0) /* enables i/o clamp_n */
-
 #define PHY_INIT_COMPLETE_TIMEOUT              10000
 
 /* set of registers with offsets different per-PHY */

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
index 2de440f0bf0236d276e70ef1f1f61a4358980803..d316a541f6287f50040270c77bd3dce8fec3aa5c 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp-usbc.c
@@ -28,38 +28,6 @@
 #include "phy-qcom-qmp.h"
 #include "phy-qcom-qmp-pcs-misc-v3.h"
 
-/* QPHY_SW_RESET bit */
-#define SW_RESET                               BIT(0)
-/* QPHY_POWER_DOWN_CONTROL */
-#define SW_PWRDN                               BIT(0)
-/* QPHY_START_CONTROL bits */
-#define SERDES_START                           BIT(0)
-#define PCS_START                              BIT(1)
-/* QPHY_PCS_STATUS bit */
-#define PHYSTATUS                              BIT(6)
-
-/* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
-/* DP PHY soft reset */
-#define SW_DPPHY_RESET                         BIT(0)
-/* mux to select DP PHY reset control, 0:HW control, 1: software reset */
-#define SW_DPPHY_RESET_MUX                     BIT(1)
-/* USB3 PHY soft reset */
-#define SW_USB3PHY_RESET                       BIT(2)
-/* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
-#define SW_USB3PHY_RESET_MUX                   BIT(3)
-
-/* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
-#define USB3_MODE                              BIT(0) /* enables USB3 mode */
-#define DP_MODE                                        BIT(1) /* enables DP mode */
-
-/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
-#define ARCVR_DTCT_EN                          BIT(0)
-#define ALFPS_DTCT_EN                          BIT(1)
-#define ARCVR_DTCT_EVENT_SEL                   BIT(4)
-
-/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
-#define IRQ_CLEAR                              BIT(0)
-
 #define PHY_INIT_COMPLETE_TIMEOUT              10000
 
 /* set of registers with offsets different per-PHY */

diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.h b/drivers/phy/qualcomm/phy-qcom-qmp.h
index d6a9c9b5ea12ec30ff66cf1deddae2b79215d9dc..d10b8f653c4b2395250917ce301c3aba003b71ad 100644 (file)
--- a/drivers/phy/qualcomm/phy-qcom-qmp.h
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.h
@@ -50,4 +50,29 @@
 
 #include "phy-qcom-qmp-pcs-v7.h"
 
+/* QPHY_SW_RESET bit */
+#define SW_RESET                               BIT(0)
+/* QPHY_POWER_DOWN_CONTROL */
+#define SW_PWRDN                               BIT(0)
+#define REFCLK_DRV_DSBL                                BIT(1) /* PCIe */
+
+/* QPHY_START_CONTROL bits */
+#define SERDES_START                           BIT(0)
+#define PCS_START                              BIT(1)
+
+/* QPHY_PCS_STATUS bit */
+#define PHYSTATUS                              BIT(6)
+#define PHYSTATUS_4_20                         BIT(7)
+
+/* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
+#define ARCVR_DTCT_EN                          BIT(0)
+#define ALFPS_DTCT_EN                          BIT(1)
+#define ARCVR_DTCT_EVENT_SEL                   BIT(4)
+
+/* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
+#define IRQ_CLEAR                              BIT(0)
+
+/* QPHY_PCS_MISC_CLAMP_ENABLE register bits */
+#define CLAMP_EN                               BIT(0) /* enables i/o clamp_n */
+
 #endif