interrupt-parent = <&asic>;
                ranges;
 
-               aips@43f00000 { /* AIPS1 */
+               bus@43f00000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips@53f00000 { /* AIPS2 */
+               bus@53f00000 { /* AIPS2 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        ranges = <0 0x1fffc000 0x4000>;
                };
 
-               aips@43f00000 { /* AIPS1 */
+               bus@43f00000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips@53f00000 { /* AIPS2 */
+               bus@53f00000 { /* AIPS2 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        cache-level = <2>;
                };
 
-               aips1: aips@43f00000 {
+               aips1: bus@43f00000 {
                        compatible = "fsl,aips", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips2: aips@53f00000 {
+               aips2: bus@53f00000 {
                        compatible = "fsl,aips", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                interrupt-parent = <&tzic>;
                ranges;
 
-               aips@50000000 { /* AIPS1 */
+               bus@50000000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips@60000000 { /* AIPS2 */
+               bus@60000000 {  /* AIPS2 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        };
                };
 
-               aips@70000000 { /* AIPS1 */
+               bus@70000000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips@80000000 { /* AIPS2 */
+               bus@80000000 {  /* AIPS2 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        clock-names = "core_clk", "mem_iface_clk";
                };
 
-               aips@50000000 { /* AIPS1 */
+               bus@50000000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips@60000000 { /* AIPS2 */
+               bus@60000000 {  /* AIPS2 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        clocks = <&clks IMX6QDL_CLK_OCRAM>;
                };
 
-               aips1: aips-bus@2000000 {
+               aips1: bus@2000000 {
                        iomuxc: iomuxc@20e0000 {
                                compatible = "fsl,imx6dl-iomuxc";
                        };
                        };
                };
 
-               aips2: aips-bus@2100000 {
+               aips2: bus@2100000 {
                        i2c4: i2c@21f8000 {
                                #address-cells = <1>;
                                #size-cells = <0>;
 
                        clocks = <&clks IMX6QDL_CLK_OCRAM>;
                };
 
-               aips-bus@2000000 { /* AIPS1 */
+               bus@2000000 { /* AIPS1 */
                        spba-bus@2000000 {
                                ecspi5: spi@2018000 {
                                        #address-cells = <1>;
 
                        status = "disabled";
                };
 
-               aips-bus@2000000 { /* AIPS1 */
+               bus@2000000 { /* AIPS1 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips-bus@2100000 { /* AIPS2 */
+               bus@2100000 { /* AIPS2 */
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        clocks = <&clks IMX6QDL_CLK_OCRAM>;
                };
 
-               aips-bus@2100000 {
+               bus@2100000 {
                        pre1: pre@21c8000 {
                                compatible = "fsl,imx6qp-pre";
                                reg = <0x021c8000 0x1000>;
 
                        arm,data-latency = <4 2 3>;
                };
 
-               aips1: aips-bus@2000000 {
+               aips1: bus@2000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips2: aips-bus@2100000 {
+               aips2: bus@2100000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        arm,data-latency = <4 2 3>;
                };
 
-               aips1: aips-bus@2000000 {
+               aips1: bus@2000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips2: aips-bus@2100000 {
+               aips2: bus@2100000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        status = "disabled";
                };
 
-               aips1: aips-bus@2000000 {
+               aips1: bus@2000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips2: aips-bus@2100000 {
+               aips2: bus@2100000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips3: aips-bus@2200000 {
+               aips3: bus@2200000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                        status = "disabled";
                };
 
-               aips1: aips-bus@2000000 {
+               aips1: bus@2000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips2: aips-bus@2100000 {
+               aips2: bus@2100000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
 
 / {
        soc {
-               aips3: aips-bus@2200000 {
+               aips3: bus@2200000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
                              <0x31006000 0x2000>;
                };
 
-               aips1: aips-bus@30000000 {
+               aips1: bus@30000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips2: aips-bus@30400000 {
+               aips2: bus@30400000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips3: aips-bus@30800000 {
+               aips3: bus@30800000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
 
        };
 
        soc {
-               aips-bus@40000000 {
+               bus@40000000 {
 
                        intc: interrupt-controller@40003000 {
                                compatible = "arm,cortex-a9-gic";
                        };
                };
 
-               aips-bus@40080000 {
+               bus@40080000 {
                        pmu@40089000 {
                                compatible = "arm,cortex-a5-pmu";
                                interrupts = <7 IRQ_TYPE_LEVEL_HIGH>;
 
                interrupt-parent = <&mscm_ir>;
                ranges;
 
-               aips0: aips-bus@40000000 {
+               aips0: bus@40000000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        };
                };
 
-               aips1: aips-bus@40080000 {
+               aips1: bus@40080000 {
                        compatible = "fsl,aips-bus", "simple-bus";
                        #address-cells = <1>;
                        #size-cells = <1>;