CLK_PCOM("tsif_ref_clk",        TSIF_REF_CLK,   NULL, 0),
        CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
        CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-       CLK_PCOM("uart_clk",    UART1_CLK,      "msm_serial.0", OFF),
-       CLK_PCOM("uart_clk",    UART2_CLK,      "msm_serial.1", 0),
-       CLK_PCOM("uart_clk",    UART3_CLK,      "msm_serial.2", OFF),
+       CLK_PCOM("core",        UART1_CLK,      "msm_serial.0", OFF),
+       CLK_PCOM("core",        UART2_CLK,      "msm_serial.1", 0),
+       CLK_PCOM("core",        UART3_CLK,      "msm_serial.2", OFF),
        CLK_PCOM("uart1dm_clk", UART1DM_CLK,    NULL, OFF),
        CLK_PCOM("uart2dm_clk", UART2DM_CLK,    NULL, 0),
        CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     "msm_hsusb", OFF),
 
        CLK_PCOM("spi_pclk",    SPI_P_CLK,      NULL, 0),
        CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
        CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-       CLK_PCOM("uart_clk",    UART2_CLK,      "msm_serial.1", 0),
+       CLK_PCOM("core",        UART2_CLK,      "msm_serial.1", 0),
        CLK_PCOM("usb_phy_clk", USB_PHY_CLK,    NULL, 0),
        CLK_PCOM("usb_hs_clk",          USB_HS_CLK,             NULL, OFF),
        CLK_PCOM("usb_hs_pclk",         USB_HS_P_CLK,           NULL, OFF),
 
        CLK_PCOM("tsif_ref_clk",        TSIF_REF_CLK,   NULL, 0),
        CLK_PCOM("tv_dac_clk",  TV_DAC_CLK,     NULL, 0),
        CLK_PCOM("tv_enc_clk",  TV_ENC_CLK,     NULL, 0),
-       CLK_PCOM("uart_clk",    UART1_CLK,      NULL, OFF),
-       CLK_PCOM("uart_clk",    UART2_CLK,      NULL, 0),
-       CLK_PCOM("uart_clk",    UART3_CLK,      "msm_serial.2", OFF),
+       CLK_PCOM("core",        UART1_CLK,      NULL, OFF),
+       CLK_PCOM("core",        UART2_CLK,      NULL, 0),
+       CLK_PCOM("core",        UART3_CLK,      "msm_serial.2", OFF),
        CLK_PCOM("uartdm_clk",  UART1DM_CLK,    NULL, OFF),
        CLK_PCOM("uartdm_clk",  UART2DM_CLK,    NULL, 0),
        CLK_PCOM("usb_hs_clk",  USB_HS_CLK,     NULL, OFF),
 
        struct msm_port *msm_port = UART_TO_MSM(port);
 
        clk_prepare_enable(msm_port->clk);
-       if (!IS_ERR(msm_port->pclk))
-               clk_prepare_enable(msm_port->pclk);
+       clk_prepare_enable(msm_port->pclk);
        msm_serial_set_mnd_regs(port);
 }
 
        switch (state) {
        case 0:
                clk_prepare_enable(msm_port->clk);
-               if (!IS_ERR(msm_port->pclk))
-                       clk_prepare_enable(msm_port->pclk);
+               clk_prepare_enable(msm_port->pclk);
                break;
        case 3:
                clk_disable_unprepare(msm_port->clk);
-               if (!IS_ERR(msm_port->pclk))
-                       clk_disable_unprepare(msm_port->pclk);
+               clk_disable_unprepare(msm_port->pclk);
                break;
        default:
                printk(KERN_ERR "msm_serial: Unknown PM state %d\n", state);
        else
                msm_port->is_uartdm = 0;
 
-       if (msm_port->is_uartdm) {
-               msm_port->clk = devm_clk_get(&pdev->dev, "gsbi_uart_clk");
-               msm_port->pclk = devm_clk_get(&pdev->dev, "gsbi_pclk");
-       } else {
-               msm_port->clk = devm_clk_get(&pdev->dev, "uart_clk");
-               msm_port->pclk = ERR_PTR(-ENOENT);
-       }
-
+       msm_port->clk = devm_clk_get(&pdev->dev, "core");
        if (IS_ERR(msm_port->clk))
                return PTR_ERR(msm_port->clk);
 
        if (msm_port->is_uartdm) {
+               msm_port->pclk = devm_clk_get(&pdev->dev, "iface");
                if (IS_ERR(msm_port->pclk))
                        return PTR_ERR(msm_port->pclk);