clk: at91: add ACR in all PLL settings

Add the ACR register to all PLL settings and provide the correct
ACR value for each PLL used in different SoCs.

Suggested-by: Mihai Sain <mihai.sain@microchip.com>
Signed-off-by: Cristian Birsan <cristian.birsan@microchip.com>
[nicolas.ferre@microchip.com: add sama7d65 and review commit message]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>

diff --git a/drivers/clk/at91/pmc.h b/drivers/clk/at91/pmc.h
index 4fb29ca111f7d4272aa6df7e1518daad758f2f02..5daa32c4cf2540d7b7ca5522dc9126e15cb5a17e 100644 (file)
--- a/drivers/clk/at91/pmc.h
+++ b/drivers/clk/at91/pmc.h
@@ -80,6 +80,7 @@ struct clk_pll_characteristics {
        u16 *icpll;
        u8 *out;
        u8 upll : 1;
+       u32 acr;
 };
 
 struct clk_programmable_layout {

diff --git a/drivers/clk/at91/sam9x60.c b/drivers/clk/at91/sam9x60.c
index db6db9e2073eb9e1a4ea2fa0993fbcaaacf23532..18baf4a256f47bdddc6b1a8af213f2c0ea02b2b3 100644 (file)
--- a/drivers/clk/at91/sam9x60.c
+++ b/drivers/clk/at91/sam9x60.c
@@ -36,6 +36,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
        .num_output = ARRAY_SIZE(plla_outputs),
        .output = plla_outputs,
        .core_output = core_outputs,
+       .acr = UL(0x00020010),
 };
 
 static const struct clk_range upll_outputs[] = {
@@ -48,6 +49,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
        .output = upll_outputs,
        .core_output = core_outputs,
        .upll = true,
+       .acr = UL(0x12023010), /* fIN = [18 MHz, 32 MHz]*/
 };
 
 static const struct clk_pll_layout pll_frac_layout = {

diff --git a/drivers/clk/at91/sam9x7.c b/drivers/clk/at91/sam9x7.c
index 740f52906f6b4315b4cb8c4be66d43ffe42db7eb..89868a0aeaba9319836f7b36aa8d322f320c8478 100644 (file)
--- a/drivers/clk/at91/sam9x7.c
+++ b/drivers/clk/at91/sam9x7.c
@@ -107,6 +107,7 @@ static const struct clk_pll_characteristics plla_characteristics = {
        .num_output = ARRAY_SIZE(plla_outputs),
        .output = plla_outputs,
        .core_output = plla_core_outputs,
+       .acr = UL(0x00020010), /* Old ACR_DEFAULT_PLLA value */
 };
 
 static const struct clk_pll_characteristics upll_characteristics = {
@@ -115,6 +116,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
        .output = upll_outputs,
        .core_output = upll_core_outputs,
        .upll = true,
+       .acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics lvdspll_characteristics = {
@@ -122,6 +124,7 @@ static const struct clk_pll_characteristics lvdspll_characteristics = {
        .num_output = ARRAY_SIZE(lvdspll_outputs),
        .output = lvdspll_outputs,
        .core_output = lvdspll_core_outputs,
+       .acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics audiopll_characteristics = {
@@ -129,6 +132,7 @@ static const struct clk_pll_characteristics audiopll_characteristics = {
        .num_output = ARRAY_SIZE(audiopll_outputs),
        .output = audiopll_outputs,
        .core_output = audiopll_core_outputs,
+       .acr = UL(0x12023010), /* fIN=[20 MHz, 32 MHz] */
 };
 
 static const struct clk_pll_characteristics plladiv2_characteristics = {
@@ -136,6 +140,7 @@ static const struct clk_pll_characteristics plladiv2_characteristics = {
        .num_output = ARRAY_SIZE(plladiv2_outputs),
        .output = plladiv2_outputs,
        .core_output = plladiv2_core_outputs,
+       .acr = UL(0x00020010),  /* Old ACR_DEFAULT_PLLA value */
 };
 
 /* Layout for fractional PLL ID PLLA. */

diff --git a/drivers/clk/at91/sama7d65.c b/drivers/clk/at91/sama7d65.c
index a5d40df8b2f272e34957861efb1cfeb2c766b504..7dee2b160ffb378b4b21d5962af4811ebe8797be 100644 (file)
--- a/drivers/clk/at91/sama7d65.c
+++ b/drivers/clk/at91/sama7d65.c
@@ -138,6 +138,7 @@ static const struct clk_pll_characteristics cpu_pll_characteristics = {
        .num_output = ARRAY_SIZE(cpu_pll_outputs),
        .output = cpu_pll_outputs,
        .core_output = core_outputs,
+       .acr = UL(0x00070010),
 };
 
 /* PLL characteristics. */
@@ -146,6 +147,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
        .num_output = ARRAY_SIZE(pll_outputs),
        .output = pll_outputs,
        .core_output = core_outputs,
+       .acr = UL(0x00070010),
 };
 
 static const struct clk_pll_characteristics lvdspll_characteristics = {
@@ -153,6 +155,7 @@ static const struct clk_pll_characteristics lvdspll_characteristics = {
        .num_output = ARRAY_SIZE(lvdspll_outputs),
        .output = lvdspll_outputs,
        .core_output = lvdspll_core_outputs,
+       .acr = UL(0x00070010),
 };
 
 static const struct clk_pll_characteristics upll_characteristics = {
@@ -160,6 +163,7 @@ static const struct clk_pll_characteristics upll_characteristics = {
        .num_output = ARRAY_SIZE(upll_outputs),
        .output = upll_outputs,
        .core_output = upll_core_outputs,
+       .acr = UL(0x12020010),
        .upll = true,
 };
 

diff --git a/drivers/clk/at91/sama7g5.c b/drivers/clk/at91/sama7g5.c
index 8385badc1c70670a680b2475aa3803a9c0a920be..1340c2b006192e5e122b460e2eca99b7ef877793 100644 (file)
--- a/drivers/clk/at91/sama7g5.c
+++ b/drivers/clk/at91/sama7g5.c
@@ -113,6 +113,7 @@ static const struct clk_pll_characteristics cpu_pll_characteristics = {
        .num_output = ARRAY_SIZE(cpu_pll_outputs),
        .output = cpu_pll_outputs,
        .core_output = core_outputs,
+       .acr = UL(0x00070010),
 };
 
 /* PLL characteristics. */
@@ -121,6 +122,7 @@ static const struct clk_pll_characteristics pll_characteristics = {
        .num_output = ARRAY_SIZE(pll_outputs),
        .output = pll_outputs,
        .core_output = core_outputs,
+       .acr = UL(0x00070010),
 };
 
 /*