drm/msm/mdp5: Stage right side hwpipes on Right-side Layer Mixer

Now that our mdp5_planes can consist of 2 hwpipes, update the
blend_setup() code to stage the right hwpipe to the left and
right LMs

Signed-off-by: Archit Taneja <architt@codeaurora.org>
Signed-off-by: Rob Clark <robdclark@gmail.com>

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
index aa67b77eea4b121c574dfc2ea22f4a5d654ac661..1276f81b413b6e0bc48cfcc04b1ac43b686b7138 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_crtc.c
@@ -239,6 +239,8 @@ static void blend_setup(struct drm_crtc *crtc)
 
        /* Collect all plane information */
        drm_atomic_crtc_for_each_plane(plane, crtc) {
+               enum mdp5_pipe right_pipe;
+
                pstate = to_mdp5_plane_state(plane->state);
                pstates[pstate->stage] = pstate;
                stage[pstate->stage][PIPE_LEFT] = mdp5_plane_pipe(plane);
@@ -249,6 +251,16 @@ static void blend_setup(struct drm_crtc *crtc)
                if (r_mixer)
                        r_stage[pstate->stage][PIPE_LEFT] =
                                                mdp5_plane_pipe(plane);
+               /*
+                * if we have a right pipe (i.e, the plane comprises of 2
+                * hwpipes, then stage the right pipe on the right side of both
+                * the layer mixers
+                */
+               right_pipe = mdp5_plane_right_pipe(plane);
+               if (right_pipe) {
+                       stage[pstate->stage][PIPE_RIGHT] = right_pipe;
+                       r_stage[pstate->stage][PIPE_RIGHT] = right_pipe;
+               }
 
                plane_cnt++;
        }

diff --git a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
index 1fdbb936877f5bc859d74c3783c6dc706dec09c0..15d78b2189359b5e961ccf3926d39e991612daa1 100644 (file)
--- a/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
+++ b/drivers/gpu/drm/msm/mdp/mdp5/mdp5_ctl.c
@@ -380,14 +380,18 @@ int mdp5_ctl_blend(struct mdp5_ctl *ctl, struct mdp5_pipeline *pipeline,
 
        for (i = start_stage; stage_cnt && i <= STAGE_MAX; i++) {
                blend_cfg |=
-                       mdp_ctl_blend_mask(stage[i][PIPE_LEFT], i);
+                       mdp_ctl_blend_mask(stage[i][PIPE_LEFT], i) |
+                       mdp_ctl_blend_mask(stage[i][PIPE_RIGHT], i);
                blend_ext_cfg |=
-                       mdp_ctl_blend_ext_mask(stage[i][PIPE_LEFT], i);
+                       mdp_ctl_blend_ext_mask(stage[i][PIPE_LEFT], i) |
+                       mdp_ctl_blend_ext_mask(stage[i][PIPE_RIGHT], i);
                if (r_mixer) {
                        r_blend_cfg |=
-                               mdp_ctl_blend_mask(r_stage[i][PIPE_LEFT], i);
+                               mdp_ctl_blend_mask(r_stage[i][PIPE_LEFT], i) |
+                               mdp_ctl_blend_mask(r_stage[i][PIPE_RIGHT], i);
                        r_blend_ext_cfg |=
-                               mdp_ctl_blend_ext_mask(r_stage[i][PIPE_LEFT], i);
+                            mdp_ctl_blend_ext_mask(r_stage[i][PIPE_LEFT], i) |
+                            mdp_ctl_blend_ext_mask(r_stage[i][PIPE_RIGHT], i);
                }
        }