drm/amdgpu: Increase soft IH ring size

Retry faults are delegated to soft IH ring and then processed by
deferred worker. Current soft IH ring size PAGE_SIZE can store 128
entries, which may overflow and drop retry faults, causes HW stucks
because the retry fault is not recovered.

Increase soft IH ring size to 8KB, enough to store 256 CAM entries
because we clear the CAM entry after handling the retry fault from soft
ring.

Define macro IH_RING_SIZE and IH_SW_RING_SIZE to remove duplicate
constant.

Show warning message if soft IH ring overflows with CAM enabled because
this should not happen.

Signed-off-by: Philip Yang <Philip.Yang@amd.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
index fceb3b384955ac023765d0616126b9c0e73a5f34..f3b0aaf3ebc69e7f90f8cf0c3f0e5d3417991669 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.c
@@ -138,6 +138,7 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
 /**
  * amdgpu_ih_ring_write - write IV to the ring buffer
  *
+ * @adev: amdgpu_device pointer
  * @ih: ih ring to write to
  * @iv: the iv to write
  * @num_dw: size of the iv in dw
@@ -145,8 +146,8 @@ void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih)
  * Writes an IV to the ring buffer using the CPU and increment the wptr.
  * Used for testing and delegating IVs to a software ring.
  */
-void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
-                         unsigned int num_dw)
+void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
+                         const uint32_t *iv, unsigned int num_dw)
 {
        uint32_t wptr = le32_to_cpu(*ih->wptr_cpu) >> 2;
        unsigned int i;
@@ -161,6 +162,9 @@ void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
        if (wptr != READ_ONCE(ih->rptr)) {
                wmb();
                WRITE_ONCE(*ih->wptr_cpu, cpu_to_le32(wptr));
+       } else if (adev->irq.retry_cam_enabled) {
+               dev_warn_once(adev->dev, "IH soft ring buffer overflow 0x%X, 0x%X\n",
+                             wptr, ih->rptr);
        }
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
index dd1c2eded6b9d2a533fed7d9cf4354e1e52d0f2d..6c6184f0dbc17e03470b1169174805186bf0df77 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_ih.h
@@ -27,6 +27,9 @@
 /* Maximum number of IVs processed at once */
 #define AMDGPU_IH_MAX_NUM_IVS  32
 
+#define IH_RING_SIZE   (256 * 1024)
+#define IH_SW_RING_SIZE        (8 * 1024)      /* enough for 256 CAM entries */
+
 struct amdgpu_device;
 struct amdgpu_iv_entry;
 
@@ -97,8 +100,8 @@ struct amdgpu_ih_funcs {
 int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
                        unsigned ring_size, bool use_bus_addr);
 void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);
-void amdgpu_ih_ring_write(struct amdgpu_ih_ring *ih, const uint32_t *iv,
-                         unsigned int num_dw);
+void amdgpu_ih_ring_write(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih,
+                         const uint32_t *iv, unsigned int num_dw);
 int amdgpu_ih_wait_on_checkpoint_process_ts(struct amdgpu_device *adev,
                                            struct amdgpu_ih_ring *ih);
 int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih);

diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
index 5273decc5753b45fff9f12f21bc6e567b13d56f3..fa6d0adcec206cacf803e349595e75a59e5d15d7 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_irq.c
@@ -493,7 +493,7 @@ void amdgpu_irq_delegate(struct amdgpu_device *adev,
                         struct amdgpu_iv_entry *entry,
                         unsigned int num_dw)
 {
-       amdgpu_ih_ring_write(&adev->irq.ih_soft, entry->iv_entry, num_dw);
+       amdgpu_ih_ring_write(adev, &adev->irq.ih_soft, entry->iv_entry, num_dw);
        schedule_work(&adev->irq.ih_soft_work);
 }
 

diff --git a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
index b02e1cef78a768ba8a7cbfe7d2d5196b49a29008..980b241200803b1f711405c1335ae559587ebce8 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/ih_v6_0.c
@@ -535,7 +535,7 @@ static int ih_v6_0_sw_init(void *handle)
         * use bus address for ih ring by psp bl */
        use_bus_addr =
                (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) ? false : true;
-       r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
+       r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
        if (r)
                return r;
 
@@ -548,7 +548,7 @@ static int ih_v6_0_sw_init(void *handle)
        /* initialize ih control register offset */
        ih_v6_0_init_register_offset(adev);
 
-       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
+       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
        if (r)
                return r;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
index eec13cb5bf75828e45c88c7715b0afb157d7605d..b6a8478dabf43cf29a428e6c0e42085fa5770001 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/navi10_ih.c
@@ -565,7 +565,7 @@ static int navi10_ih_sw_init(void *handle)
                use_bus_addr = false;
        else
                use_bus_addr = true;
-       r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
+       r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
        if (r)
                return r;
 
@@ -578,7 +578,7 @@ static int navi10_ih_sw_init(void *handle)
        /* initialize ih control registers offset */
        navi10_ih_init_register_offset(adev);
 
-       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
+       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
        if (r)
                return r;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
index 1e83db0c5438d0c07b27bf1540ad6b4bdf2bc61e..d364c6dd152c33b7fc1fbc614668b2dd4ffe223a 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega10_ih.c
@@ -485,7 +485,7 @@ static int vega10_ih_sw_init(void *handle)
        if (r)
                return r;
 
-       r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, true);
+       r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, true);
        if (r)
                return r;
 
@@ -510,7 +510,7 @@ static int vega10_ih_sw_init(void *handle)
        /* initialize ih control registers offset */
        vega10_ih_init_register_offset(adev);
 
-       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, true);
+       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, true);
        if (r)
                return r;
 

diff --git a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
index 4d719df376a7224dba72c2cf880cd18e5e8d2044..544ee55a22da662b17b53b49ecee926f41d5f71f 100644 (file)
--- a/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
+++ b/drivers/gpu/drm/amd/amdgpu/vega20_ih.c
@@ -539,7 +539,7 @@ static int vega20_ih_sw_init(void *handle)
            (adev->ip_versions[OSSSYS_HWIP][0] == IP_VERSION(4, 4, 2)))
                use_bus_addr = false;
 
-       r = amdgpu_ih_ring_init(adev, &adev->irq.ih, 256 * 1024, use_bus_addr);
+       r = amdgpu_ih_ring_init(adev, &adev->irq.ih, IH_RING_SIZE, use_bus_addr);
        if (r)
                return r;
 
@@ -565,7 +565,7 @@ static int vega20_ih_sw_init(void *handle)
        /* initialize ih control registers offset */
        vega20_ih_init_register_offset(adev);
 
-       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, PAGE_SIZE, use_bus_addr);
+       r = amdgpu_ih_ring_init(adev, &adev->irq.ih_soft, IH_SW_RING_SIZE, use_bus_addr);
        if (r)
                return r;