static int rockchip_rk3399_pll_wait_lock(struct rockchip_clk_pll *pll)
 {
        u32 pllcon;
-       int delay = 24000000;
+       int ret;
 
-       /* poll check the lock status in rk3399 xPLLCON2 */
-       while (delay > 0) {
-               pllcon = readl_relaxed(pll->reg_base + RK3399_PLLCON(2));
-               if (pllcon & RK3399_PLLCON2_LOCK_STATUS)
-                       return 0;
+       /*
+        * Lock time typical 250, max 500 input clock cycles @24MHz
+        * So define a very safe maximum of 1000us, meaning 24000 cycles.
+        */
+       ret = readl_relaxed_poll_timeout(pll->reg_base + RK3399_PLLCON(2),
+                                        pllcon,
+                                        pllcon & RK3399_PLLCON2_LOCK_STATUS,
+                                        0, 1000);
+       if (ret)
+               pr_err("%s: timeout waiting for pll to lock\n", __func__);
 
-               delay--;
-       }
-
-       pr_err("%s: timeout waiting for pll to lock\n", __func__);
-       return -ETIMEDOUT;
+       return ret;
 }
 
 static void rockchip_rk3399_pll_get_params(struct rockchip_clk_pll *pll,